- 02 Jun, 2020 1 commit
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Lukas Posadka authored
- UART4 assigned to the Cortex-A53 cluster instead of M4 - DDR memmap size updated to cover also the 4G SX8M variant
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- 17 Jul, 2019 1 commit
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Nitin Garg authored
Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 91e7cb2b)
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- 12 Jul, 2019 1 commit
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Jacky Bai authored
Explict memory barrier(DSB) is necessary to make sure other cores observe the correct flags updated by the primary core before the primary begins doing DRAM DVFS. Signed-off-by:
Jacky Bai <ping.bai@nxp.com> (cherry picked from commit dac8d677)
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- 01 Apr, 2019 2 commits
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Ji Luo authored
This patch fix type mismatch and dead codes in gpio functions. Test: build and boot on AIY 1G DDR board. Signed-off-by:
Ji Luo <ji.luo@nxp.com>
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Ji Luo authored
TEE will be loaded to 0x7e000000 for AIY 1G ddr board, distinguish different baseboard by the board id and set different tee address accordingly. Test: build and boot ok for both AIY 1G and 3G ddr board. Signed-off-by:
Ji Luo <ji.luo@nxp.com>
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- 21 Mar, 2019 1 commit
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Jacky Bai authored
Fix the ddr4 retention exit hang caused by improper init flow. Signed-off-by:
Jacky Bai <ping.bai@nxp.com> (cherry picked from commit ae126e71)
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- 14 Mar, 2019 1 commit
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Jacky Bai authored
Clean up & Fix the license issue Signed-off-by:
Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 1a43400e)
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- 13 Mar, 2019 3 commits
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Jacky Bai authored
clean up & fix the license issue Signed-off-by:
Jacky Bai <ping.bai@nxp.com> (cherry picked from commit ec9654ad)
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Anson Huang authored
This reverts commit d4a0970c. SCFW already supported OCRAM retention, so no need to change primary CPU's entry. (cherry picked from commit 66949278)
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Anson Huang authored
This reverts commit 8673a8e5. SCFW already supported OCRAM retention, so no need to change primary CPU's boot entry. (cherry picked from commit e49e1c05)
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- 05 Mar, 2019 1 commit
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Ji Luo authored
Config the base address(0xfe00_0000) and size(0x200_0000) for Trusty OS to enable it on AIY board. Test: Trusty OS boots up ok. Change-Id: Ia7ed33447fc7b84ba2005d332c1379564fc647c1 Signed-off-by:
Ji Luo <ji.luo@nxp.com>
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- 04 Mar, 2019 1 commit
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Anson Huang authored
MU_SR register bit[30] is cold boot flag passed from SCU, w0 is random value and would clear the flag incorrectly, and cause system partition reboot fail if Linux is in suspend. So this patch initializes it to 0x80000000 which is exactly the same with first time board power up before writting to MU_SR register. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 3bbb1bc8)
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- 27 Feb, 2019 6 commits
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Anson Huang authored
The boot device info should be kept during partition reboot, the boot device ownership is changed after partition management in ATF, so calling sc_pm_set_boot_parm() with boot device parameter will fail in PSCI initialization phase, moving it to bl31_early_platform_setup2() can make it work, correct them. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit d0c4a4e2c2d2618bef7c469c11ebeeb98174630a)
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Ye Li authored
On iMX8 Rev A the OCRAM is used to pass over ROM info, and u-boot needs to access it. So we can't assign the OCRAM to ATF partition. This will cause boot hang. Rev A does not support SPL, so it is ok to not protect the OCRAM. Signed-off-by:
Ye Li <ye.li@nxp.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com> (cherry picked from commit c9a168bf)
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Anson Huang authored
With SPL running on OCRAM, when linux suspend, OCRAM will lose power and if partition reboot is started from SPL, system will hang as the OCRAM data lost, so for partition reboot, the CPU boot entry can be set to be from ATF BL31 entry directly, SCFW exposes such API for this scenario. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit d4a0970c)
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Anson Huang authored
Update SCFW APIs to SCFW commit: e7a99eb96207 ("SCF-351: Add API to change boot parms.") Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 22a97387)
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Anson Huang authored
With partition reboot enabled, console_list variable which is located in data section is NOT reset, system will be busy looping in early console operation of flush_loop() if console_list is NOT 0 while HW console is NOT initialized, so we have to clear this variable to make partition reboot work. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 8328fcf8)
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Anson Huang authored
For i.MX SoCs with system controller inside, partition reboot is supported, and when reboot, CPU will be reset to ATF entry directly, the data section is NOT reset, console_list variable needs to be initialized to 0 to make it work, otherwise, system will be busy looping in flush_loop(). So expose console_list for i.MX platforms to initialize this variable. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 7802cd70)
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- 26 Feb, 2019 1 commit
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Jacky Bai authored
currently MAX_XLAT_TABLE size is not enough for debug build, so enlarge it to make it works. Signed-off-by:
Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 95095ba9)
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- 21 Feb, 2019 1 commit
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Nitin Garg authored
The issue of A53 cluster runtime power ON/OFF has been identified as fifo reset issue, and there is software workaround to avoid such issue and A53 cluster now can be turned OFF. Signed-off-by:
Nitin Garg <nitin.garg@nxp.com> Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 77de1ee8)
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- 15 Feb, 2019 1 commit
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Anson Huang authored
Update SCFW APIs to SCFW commit: 004247e14afc ("SCF-341 Fix bug in setting large slice clock divider") Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit b6c41566)
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- 12 Feb, 2019 2 commits
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Haoran.Wang authored
Due imx8qm_mek's UART0_RTS_B and UART0_CTS_0 pad reuse to be the UART2 for base bard which operated by M4_1, so don't touch these two pads in ATF. Signed-off-by:
Haoran.Wang <elven.wang@nxp.com> Acked-by:
Pete Zhang <pete.zhang@nxp.com>
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Anson Huang authored
GICR_WAKER.ProcessorSleep can only be set to zero when: — GICR_WAKER.Sleep bit[0] == 0. — GICR_WAKER.Quiescent bit[31] == 0. On some platforms, when system reboot with GIC in sleep mode but with power ON, such as on NXP's i.MX8QM, Linux kernel enters suspend but could be requested to reboot, and GIC is in sleep mode and it is inside a power domain which is ON in this scenario, when CPU reset, the GIC driver trys to set CORE's redistributor interface to awake, with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] both set, the ProcessorSleep bit[1] will never be clear and cause system hang. This patch makes sure GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] are both zeor before clearing ProcessorSleep bit[1]. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 4436f3a4)
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- 11 Feb, 2019 2 commits
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Anson Huang authored
Enable IRQ steer wakeup source support for Linux kernel wakeup sources like debug UART wakeup etc.. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com>
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Ye Li authored
Because the partition reboot won't reload the first level bootloader (SPL), the SPL won't be authenticated. Users can corrupt the SPL image to break the boot trust chain in secure boot if we don't protect that OCRAM area. This patch configures the memory area from 0x0 to 0x118000 only accessed by secure partition (ATF and OPTEE). Non-secure partitions (u-boot and kernel) can't access it. Signed-off-by:
Ye Li <ye.li@nxp.com> (cherry picked from commit 1eff7d3ef6f121782e56bb1807744ede48b8580b)
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- 10 Feb, 2019 1 commit
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Anson Huang authored
Update SCFW APIs to SCFW commit: 5c03342369e8 ("SCF-105: Change links in wiki index.") Signed-off-by:
Anson Huang <Anson.Huang@nxp.com>
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- 07 Feb, 2019 13 commits
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Silvano di Ninno authored
If ATF loads OP-TEE, it will pass OP-TEE base address and size to the u-boot through boot information. This will help u-boot update device tree accordingly. Note that u-boot on i.MX 8QxP does not need this information to configure memory mapping. Query to the SC Firmware is used instead. Signed-off-by:
Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit 70c1d422e520f8f1c201a7e4fe22870832240db7)
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Silvano di Ninno authored
Configure OP-TEE Share memory to be accessible by OS. Signed-off-by:
Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit b2d0c8530c75bb77450372114229cadd8555780b)
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Silvano di Ninno authored
Fix size of BL32 (currently is 32MB). Signed-off-by:
Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit 5087a9cda77b3c6a5566e4a9520ab476bfe9154a)
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Silvano di Ninno authored
Reuse Trusty support for OP-TEE Signed-off-by:
Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit a558c8fb87171f4ebcc44bb0b8aa699c989a2a7d)
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Silvano di Ninno authored
If ATF loads OP-TEE, it will pass OP-TEE base address and size to the u-boot through boot information. This will help u-boot update device tree accordingly. Note that u-boot on i.MX 8QxP does not need this information to configure memory mapping. Query to the SC Firmware is used instead Signed-off-by:
Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit e80fe229192578120a3ba98ae26fd3dbf121538f)
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Silvano di Ninno authored
configure OP-TEE Share memory to be accessible by OS. Signed-off-by:
Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit 0b5eeb7e0dbe50ebd7f3d0ce66047569504e9d52)
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Silvano di Ninno authored
fix size of BL32 (currently is 32MB) Signed-off-by:
Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit f66251dedef31750ff7be4c0e404b77d0a8fb1c4)
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Silvano di Ninno authored
reuse Trusty support for OP-TEE Signed-off-by:
Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit 6e2885a262b94bdeb8face851012f58ed32e86a9)
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Ji Luo authored
JR0 and JR1 of CAAM are owned by SECO, only kick the power of JR2 and JR3 here and assign the resources to be accessed by secure world. Signed-off-by:
Ji Luo <ji.luo@nxp.com> (cherry picked from commit 4f00df596a80cb4b4539d228332d976cf38d4183)
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Luo Ji authored
Tee(Trusty Os) will be stored in fit for Android and Android Auto so we don't need to copy it anymore, this will save some boot time. Signed-off-by:
Luo Ji <ji.luo@nxp.com> (cherry picked from commit 4cb7c6fbd251ae2603f470fb23c526f73acbf7f9)
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Haoran.Wang authored
The Trusty OS binary will be installed into container.img and loaded into 0x84000000. Due Trusty OS addresss is in 0xfe000000 which ROM cannot reach, so use ATF to copy it into the target address. Mapped the BL32 code into MMU due the Trusty SPD need to check the code status and decide the CPU executing mode. To reserve and protect the memory for secure world, modify the partition code to keep BL32 spaces in secure_part. Signed-off-by:
Haoran.Wang <elven.wang@nxp.com> Reviewed-by:
Ye Li <ye.li@nxp.com> (cherry picked from commit d305ece47bf3e90b5008bf5932583ee2a772650b)
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Peng Fan authored
With flash_uboot_cm4ddr in imx-mkimage, the m4 code will access ddr. However after m4 core moved to non-secure partition, the ddr memory is still in secure partition. Then m4 core will fault. So postpone moving resources including m4 core, until other resources, such as memory/pin moved to non-secure partition. Signed-off-by:
Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1c8ce0ad5f583ec41026d4ab5bef622f1b45aecd) (cherry picked from commit 5b026e05b8f71b3d86da0953c5ca196d5ba5cc66)
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Peng Fan authored
With default configuration, M4 and A35 in one partition, M4 is loaded by ROM. "err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);" M4 core will first be moved to non-secure OS part, then the resource used by M4 will be moved to non-secure OS part later. But before the resource be moved to non-secure OS part, M4 core is still running, so a non-secure M4 core access a secure resource will trigger error in M4 side. First mark M4 core as non-movable, after all other resoures moved to OS part, move M4 to OS part. No need to check whether M4 is created a new partition by SCFW, if a partition already created, the call to mark M4 as non-removable will fail, because it M4 is in its own partition. Signed-off-by:
Peng Fan <peng.fan@nxp.com> (cherry picked from commit 44e209cb87f078abc78839c5e138aae5122ddd78)
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- 25 Jan, 2019 1 commit
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Jacky Bai authored
Add the dram pll lock check to make the pll is already locked bofore dram exit from retention mode. addtionally, the DDR4 reset flow need some change to make sure DRAM exit retention safely. Signed-off-by:
Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 858e2141138d87fe6072f8ba0321b3963ae9630c)
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