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Ranjani Vaidyanathan authored
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it can run at 270MHz on MX6DL/S. This is required for improving VPU performance. Change AXI_CLK to be sourced from periph_clk just before the DDR freq is going to be dropped to 24MHz/50MHz. Change it back to PLL3_PFD1_540 when the DDR freq is back at 400MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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