Commit 2e4bd833 authored by Jason Chen's avatar Jason Chen Committed by Jason Liu

ENGR00141217-5 IPU\VPU\GPU: upgrade to 2.6.38

Add drivers/mxc
Add drivers/video/mxc
Add drivers/media/mxc
fb device: change acquire_console_sem to console_lock
And release_console_sem to console_unlock
Add DMA Zone support
Add TVE driver, add regulator
Add hdmi support
Add VPU

Fix build error
ioctl --> unlocked_ioctl
DECLARE_MUTEX --> DEFINE_SEMAPHORE
Signed-off-by: default avatarJason Chen <b02280@freescale.com>
Signed-off-by: default avatarRichard Zhao <richard.zhao@freescale.com>
parent 8029d5b1
......@@ -126,4 +126,6 @@ source "drivers/hwspinlock/Kconfig"
source "drivers/clocksource/Kconfig"
source "drivers/mxc/Kconfig"
endmenu
......@@ -96,6 +96,7 @@ obj-y += lguest/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_CPU_IDLE) += cpuidle/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_ARCH_MXC) += mxc/
obj-$(CONFIG_MEMSTICK) += memstick/
obj-y += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
......
......@@ -618,6 +618,56 @@ config VIDEO_W9966
Check out <file:Documentation/video4linux/w9966.txt> for more
information.
config VIDEO_MXC_CAMERA
tristate "MXC Video For Linux Camera"
depends on VIDEO_DEV && ARCH_MXC
default y
---help---
This is the video4linux2 capture driver based on MXC IPU/eMMA module.
source "drivers/media/video/mxc/capture/Kconfig"
config VIDEO_MXC_OUTPUT
tristate "MXC Video For Linux Video Output"
depends on VIDEO_DEV && ARCH_MXC
default y
---help---
This is the video4linux2 output driver based on MXC IPU/eMMA module.
source "drivers/media/video/mxc/output/Kconfig"
config VIDEO_MXS_PXP
tristate "MXS PxP"
depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MXS
select VIDEOBUF_DMA_CONTIG
---help---
This is a video4linux driver for the Freescale PxP
(Pixel Pipeline). This module supports output overlay of
the MXS framebuffer on a video stream.
To compile this driver as a module, choose M here: the
module will be called pxp.
config VIDEO_MXC_PXP_V4L2
tristate "MXC PxP V4L2 driver"
depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MX5
select VIDEOBUF_DMA_CONTIG
---help---
This is a video4linux driver for the Freescale PxP
(Pixel Pipeline). This module supports output overlay of
the MXC framebuffer on a video stream.
To compile this driver as a module, choose M here.
config VIDEO_MXC_OPL
tristate
depends on VIDEO_DEV && ARCH_MXC
default n
---help---
This is the ARM9-optimized OPL (Open Primitives Library) software
rotation/mirroring implementation. It may be used by eMMA video
capture or output device.
source "drivers/media/video/cpia2/Kconfig"
config VIDEO_VINO
......
......@@ -87,6 +87,15 @@ obj-$(CONFIG_SOC_CAMERA_TW9910) += tw9910.o
# And now the v4l2 drivers:
obj-$(CONFIG_VIDEO_MXC_IPU_CAMERA) += mxc/capture/
obj-$(CONFIG_VIDEO_MXC_CSI_CAMERA) += mxc/capture/
obj-$(CONFIG_VIDEO_MXC_IPU_OUTPUT) += mxc/output/
obj-$(CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT) += mxc/output/
obj-$(CONFIG_VIDEO_MXC_EMMA_OUTPUT) += mxc/output/
obj-$(CONFIG_VIDEO_MXC_PXP_V4L2) += mxc/output/
obj-$(CONFIG_VIDEO_MXC_OPL) += mxc/opl/
obj-$(CONFIG_VIDEO_PXP) += pxp.o
obj-$(CONFIG_VIDEO_MXS_PXP) += mxs_pxp.o
obj-$(CONFIG_VIDEO_BT848) += bt8xx/
obj-$(CONFIG_VIDEO_ZORAN) += zoran/
obj-$(CONFIG_VIDEO_CQCAM) += c-qcam.o
......
if VIDEO_MXC_CAMERA
menu "MXC Camera/V4L2 PRP Features support"
config VIDEO_MXC_IPU_CAMERA
bool
depends on VIDEO_MXC_CAMERA && MXC_IPU
default y
config VIDEO_MXC_EMMA_CAMERA
tristate "MX27 eMMA support"
depends on VIDEO_MXC_CAMERA && MXC_EMMA && FB_MXC_SYNC_PANEL
select VIDEO_MXC_OPL
default y
config VIDEO_MXC_CSI_CAMERA
tristate "MX25 CSI camera support"
depends on !VIDEO_MXC_EMMA_CAMERA
config VIDEO_MXC_CSI_DMA
bool "CSI-DMA Still Image Capture support"
depends on VIDEO_MXC_EMMA_CAMERA
default n
---help---
Use CSI-DMA method instead of CSI-PrP link to capture still image. This allows
to use less physical contiguous memory to capture big resolution still image. But
with this method the CSC (Color Space Conversion) and resize are not supported.
If unsure, say N.
choice
prompt "Select Camera/TV Decoder"
default MXC_CAMERA_OV3640
depends on VIDEO_MXC_CAMERA
config MXC_CAMERA_MC521DA
tristate "Magnachip mc521da camera support"
select I2C_MXC
depends on VIDEO_MXC_EMMA_CAMERA
---help---
If you plan to use the mc521da Camera with your MXC system, say Y here.
config MXC_EMMA_CAMERA_MICRON111
tristate "Micron mt9v111 camera support with eMMA"
select I2C_MXC
depends on VIDEO_MXC_EMMA_CAMERA
---help---
If you plan to use the mt9v111 Camera with your MXC system, say Y here.
config MXC_CAMERA_OV2640_EMMA
tristate "OmniVision ov2640 camera support with eMMA"
depends on VIDEO_MXC_EMMA_CAMERA
---help---
If you plan to use the ov2640 Camera with your MXC system, say Y here.
config MXC_CAMERA_MICRON111
tristate "Micron mt9v111 camera support"
select I2C_MXC
depends on ! VIDEO_MXC_EMMA_CAMERA
---help---
If you plan to use the mt9v111 Camera with your MXC system, say Y here.
config MXC_CAMERA_OV2640
tristate "OmniVision ov2640 camera support"
depends on !VIDEO_MXC_EMMA_CAMERA
---help---
If you plan to use the ov2640 Camera with your MXC system, say Y here.
config MXC_CAMERA_OV3640
tristate "OmniVision ov3640 camera support"
depends on !VIDEO_MXC_EMMA_CAMERA
---help---
If you plan to use the ov3640 Camera with your MXC system, say Y here.
config MXC_CAMERA_OV5640
tristate "OmniVision ov5640 camera support"
depends on !VIDEO_MXC_EMMA_CAMERA
---help---
If you plan to use the ov5640 Camera with your MXC system, say Y here.
config MXC_CAMERA_OV5642
tristate "OmniVision ov5642 camera support"
depends on !VIDEO_MXC_EMMA_CAMERA
---help---
If you plan to use the ov5642 Camera with your MXC system, say Y here.
config MXC_TVIN_ADV7180
tristate "Analog Device adv7180 TV Decoder Input support"
depends on (MACH_MX35_3DS || MACH_MX51_3DS)
---help---
If you plan to use the adv7180 video decoder with your MXC system, say Y here.
endchoice
config MXC_IPU_PRP_VF_SDC
tristate "Pre-Processor VF SDC library"
depends on VIDEO_MXC_IPU_CAMERA && FB_MXC_SYNC_PANEL
default y
---help---
Use case PRP_VF_SDC:
Preprocessing image from smart sensor for viewfinder and
displaying it on synchronous display with SDC use case.
If SDC BG is selected, Rotation will not be supported.
CSI -> IC (PRP VF) -> MEM
MEM -> IC (ROT) -> MEM
MEM -> SDC (FG/BG)
config MXC_IPU_PRP_ENC
tristate "Pre-processor Encoder library"
depends on VIDEO_MXC_IPU_CAMERA
default y
---help---
Use case PRP_ENC:
Preprocessing image from smart sensor for encoder.
CSI -> IC (PRP ENC) -> MEM
config MXC_IPU_CSI_ENC
tristate "IPU CSI Encoder library"
depends on VIDEO_MXC_IPU_CAMERA
default y
---help---
Use case IPU_CSI_ENC:
Get raw image with CSI from smart sensor for encoder.
CSI -> MEM
endmenu
endif
ifeq ($(CONFIG_VIDEO_MXC_IPU_CAMERA),y)
obj-$(CONFIG_VIDEO_MXC_CAMERA) += mxc_v4l2_capture.o
obj-$(CONFIG_MXC_IPU_PRP_VF_SDC) += ipu_prp_vf_sdc.o ipu_prp_vf_sdc_bg.o
obj-$(CONFIG_MXC_IPU_PRP_ENC) += ipu_prp_enc.o ipu_still.o
obj-$(CONFIG_MXC_IPU_CSI_ENC) += ipu_csi_enc.o ipu_still.o
endif
obj-$(CONFIG_VIDEO_MXC_CSI_CAMERA) += fsl_csi.o csi_v4l2_capture.o
mx27_capture-objs := mx27_prphw.o mx27_prpsw.o emma_v4l2_capture.o
obj-$(CONFIG_VIDEO_MXC_EMMA_CAMERA) += mx27_csi.o mx27_capture.o
mc521da_camera-objs := mc521da.o sensor_clock.o
obj-$(CONFIG_MXC_CAMERA_MC521DA) += mc521da_camera.o
emma_mt9v111_camera-objs := emma_mt9v111.o sensor_clock.o
obj-$(CONFIG_MXC_EMMA_CAMERA_MICRON111) += emma_mt9v111_camera.o
mt9v111_camera-objs := mt9v111.o sensor_clock.o
obj-$(CONFIG_MXC_CAMERA_MICRON111) += mt9v111_camera.o
hv7161_camera-objs := hv7161.o sensor_clock.o
obj-$(CONFIG_MXC_CAMERA_HV7161) += hv7161_camera.o
s5k3aaex_camera-objs := s5k3aaex.o sensor_clock.o
obj-$(CONFIG_MXC_CAMERA_S5K3AAEX) += s5k3aaex_camera.o
emma_ov2640_camera-objs := emma_ov2640.o sensor_clock.o
obj-$(CONFIG_MXC_CAMERA_OV2640_EMMA) += emma_ov2640_camera.o
ov2640_camera-objs := ov2640.o sensor_clock.o
obj-$(CONFIG_MXC_CAMERA_OV2640) += ov2640_camera.o
ov3640_camera-objs := ov3640.o sensor_clock.o
obj-$(CONFIG_MXC_CAMERA_OV3640) += ov3640_camera.o
ov5640_camera-objs := ov5640.o sensor_clock.o
obj-$(CONFIG_MXC_CAMERA_OV5640) += ov5640_camera.o
ov5642_camera-objs := ov5642.o sensor_clock.o
obj-$(CONFIG_MXC_CAMERA_OV5642) += ov5642_camera.o
adv7180_tvin-objs := adv7180.o
obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o
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/*
* Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file fsl_csi.c, this file is derived from mx27_csi.c
*
* @brief mx25 CMOS Sensor interface functions
*
* @ingroup CSI
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <mach/clock.h>
#include "mxc_v4l2_capture.h"
#include "fsl_csi.h"
static bool g_csi_mclk_on;
static csi_irq_callback_t g_callback;
static void *g_callback_data;
static struct clk csi_mclk;
static irqreturn_t csi_irq_handler(int irq, void *data)
{
cam_data *cam = (cam_data *) data;
unsigned long status = __raw_readl(CSI_CSISR);
unsigned long cr3 = __raw_readl(CSI_CSICR3);
unsigned int frame_count = (cr3 >> 16) & 0xFFFF;
__raw_writel(status, CSI_CSISR);
if (status & BIT_SOF_INT) {
/* reflash the embeded DMA controller */
if (frame_count % 2 == 1)
__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
}
if (status & BIT_DMA_TSF_DONE_FB1) {
if (cam->capture_on) {
cam->ping_pong_csi = 1;
cam->enc_callback(0, cam);
} else {
cam->still_counter++;
wake_up_interruptible(&cam->still_queue);
}
}
if (status & BIT_DMA_TSF_DONE_FB2) {
if (cam->capture_on) {
cam->ping_pong_csi = 2;
cam->enc_callback(0, cam);
} else {
cam->still_counter++;
wake_up_interruptible(&cam->still_queue);
}
}
if (g_callback)
g_callback(g_callback_data, status);
pr_debug("CSI status = 0x%08lX\n", status);
return IRQ_HANDLED;
}
static void csihw_reset_frame_count(void)
{
__raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, CSI_CSICR3);
}
static void csihw_reset(void)
{
csihw_reset_frame_count();
__raw_writel(CSICR1_RESET_VAL, CSI_CSICR1);
__raw_writel(CSICR2_RESET_VAL, CSI_CSICR2);
__raw_writel(CSICR3_RESET_VAL, CSI_CSICR3);
}
/*!
* csi_init_interface
* Init csi interface
*/
void csi_init_interface(void)
{
unsigned int val = 0;
unsigned int imag_para;
val |= BIT_SOF_POL;
val |= BIT_REDGE;
val |= BIT_GCLK_MODE;
val |= BIT_HSYNC_POL;
val |= BIT_PACK_DIR;
val |= BIT_FCC;
val |= BIT_SWAP16_EN;
val |= 1 << SHIFT_MCLKDIV;
__raw_writel(val, CSI_CSICR1);
imag_para = (640 << 16) | 960;
__raw_writel(imag_para, CSI_CSIIMAG_PARA);
val = 0x1010;
val |= BIT_DMA_REFLASH_RFF;
__raw_writel(val, CSI_CSICR3);
}
EXPORT_SYMBOL(csi_init_interface);
/*!
* csi_enable_mclk
*
* @param src enum define which source to control the clk
* CSI_MCLK_VF CSI_MCLK_ENC CSI_MCLK_RAW CSI_MCLK_I2C
* @param flag true to enable mclk, false to disable mclk
* @param wait true to wait 100ms make clock stable, false not wait
*
* @return 0 for success
*/
int32_t csi_enable_mclk(int src, bool flag, bool wait)
{
if (flag == true) {
csi_mclk_enable();
if (wait == true)
msleep(10);
pr_debug("Enable csi clock from source %d\n", src);
g_csi_mclk_on = true;
} else {
csi_mclk_disable();
pr_debug("Disable csi clock from source %d\n", src);
g_csi_mclk_on = false;
}
return 0;
}
EXPORT_SYMBOL(csi_enable_mclk);
/*!
* csi_read_mclk_flag
*
* @return gcsi_mclk_source
*/
int csi_read_mclk_flag(void)
{
return 0;
}
EXPORT_SYMBOL(csi_read_mclk_flag);
void csi_start_callback(void *data)
{
cam_data *cam = (cam_data *) data;
if (request_irq(MXC_INT_CSI, csi_irq_handler, 0, "csi", cam) < 0)
pr_debug("CSI error: irq request fail\n");
}
EXPORT_SYMBOL(csi_start_callback);
void csi_stop_callback(void *data)
{
cam_data *cam = (cam_data *) data;
free_irq(MXC_INT_CSI, cam);
}
EXPORT_SYMBOL(csi_stop_callback);
void csi_enable_int(int arg)
{
unsigned long cr1 = __raw_readl(CSI_CSICR1);
cr1 |= BIT_SOF_INTEN;
if (arg == 1) {
/* still capture needs DMA intterrupt */
cr1 |= BIT_FB1_DMA_DONE_INTEN;
cr1 |= BIT_FB2_DMA_DONE_INTEN;
}
__raw_writel(cr1, CSI_CSICR1);
}
EXPORT_SYMBOL(csi_enable_int);
void csi_disable_int(void)
{
unsigned long cr1 = __raw_readl(CSI_CSICR1);
cr1 &= ~BIT_SOF_INTEN;
cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
__raw_writel(cr1, CSI_CSICR1);
}
EXPORT_SYMBOL(csi_disable_int);
void csi_set_16bit_imagpara(int width, int height)
{
int imag_para = 0;
unsigned long cr3 = __raw_readl(CSI_CSICR3);
imag_para = (width << 16) | (height * 2);
__raw_writel(imag_para, CSI_CSIIMAG_PARA);
/* reflash the embeded DMA controller */
__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
}
EXPORT_SYMBOL(csi_set_16bit_imagpara);
void csi_set_12bit_imagpara(int width, int height)
{
int imag_para = 0;
unsigned long cr3 = __raw_readl(CSI_CSICR3);
imag_para = (width << 16) | (height * 3 / 2);
__raw_writel(imag_para, CSI_CSIIMAG_PARA);
/* reflash the embeded DMA controller */
__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
}
EXPORT_SYMBOL(csi_set_12bit_imagpara);
static void csi_mclk_recalc(struct clk *clk)
{
u32 div;
unsigned long rate;
div = (__raw_readl(CSI_CSICR1) & BIT_MCLKDIV) >> SHIFT_MCLKDIV;
if (div == 0)
div = 1;
else
div = div * 2;
rate = clk_get_rate(clk->parent) / div;
clk_set_rate(clk, rate);
}
void csi_mclk_enable(void)
{
__raw_writel(__raw_readl(CSI_CSICR1) | BIT_MCLKEN, CSI_CSICR1);
}
void csi_mclk_disable(void)
{
__raw_writel(__raw_readl(CSI_CSICR1) & ~BIT_MCLKEN, CSI_CSICR1);
}
int32_t __init csi_init_module(void)
{
int ret = 0;
struct clk *per_clk;
csihw_reset();
csi_init_interface();
per_clk = clk_get(NULL, "csi_clk");
if (IS_ERR(per_clk))
return PTR_ERR(per_clk);
clk_put(per_clk);
csi_mclk.parent = per_clk;
clk_enable(per_clk);
csi_mclk_recalc(&csi_mclk);
return ret;
}
void __exit csi_cleanup_module(void)
{
clk_disable(&csi_mclk);
}
module_init(csi_init_module);
module_exit(csi_cleanup_module);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("fsl CSI driver");
MODULE_LICENSE("GPL");
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file fsl_csi.h
*
* @brief mx25 CMOS Sensor interface functions
*
* @ingroup CSI
*/
#ifndef MX25_CSI_H
#define MX25_CSI_H
#include <linux/io.h>
#include <mach/hardware.h>
/* reset values */
#define CSICR1_RESET_VAL 0x40000800
#define CSICR2_RESET_VAL 0x0
#define CSICR3_RESET_VAL 0x0
/* csi control reg 1 */
#define BIT_SWAP16_EN (0x1 << 31)
#define BIT_EXT_VSYNC (0x1 << 30)
#define BIT_EOF_INT_EN (0x1 << 29)
#define BIT_PRP_IF_EN (0x1 << 28)
#define BIT_CCIR_MODE (0x1 << 27)
#define BIT_COF_INT_EN (0x1 << 26)
#define BIT_SF_OR_INTEN (0x1 << 25)
#define BIT_RF_OR_INTEN (0x1 << 24)
#define BIT_SFF_DMA_DONE_INTEN (0x1 << 22)
#define BIT_STATFF_INTEN (0x1 << 21)
#define BIT_FB2_DMA_DONE_INTEN (0x1 << 20)
#define BIT_FB1_DMA_DONE_INTEN (0x1 << 19)
#define BIT_RXFF_INTEN (0x1 << 18)
#define BIT_SOF_POL (0x1 << 17)
#define BIT_SOF_INTEN (0x1 << 16)
#define BIT_MCLKDIV (0xF << 12)
#define BIT_HSYNC_POL (0x1 << 11)
#define BIT_CCIR_EN (0x1 << 10)
#define BIT_MCLKEN (0x1 << 9)
#define BIT_FCC (0x1 << 8)
#define BIT_PACK_DIR (0x1 << 7)
#define BIT_CLR_STATFIFO (0x1 << 6)
#define BIT_CLR_RXFIFO (0x1 << 5)
#define BIT_GCLK_MODE (0x1 << 4)
#define BIT_INV_DATA (0x1 << 3)
#define BIT_INV_PCLK (0x1 << 2)
#define BIT_REDGE (0x1 << 1)
#define BIT_PIXEL_BIT (0x1 << 0)
#define SHIFT_MCLKDIV 12
/* control reg 3 */
#define BIT_FRMCNT (0xFFFF << 16)
#define BIT_FRMCNT_RST (0x1 << 15)
#define BIT_DMA_REFLASH_RFF (0x1 << 14)
#define BIT_DMA_REFLASH_SFF (0x1 << 13)
#define BIT_DMA_REQ_EN_RFF (0x1 << 12)
#define BIT_DMA_REQ_EN_SFF (0x1 << 11)
#define BIT_STATFF_LEVEL (0x7 << 8)
#define BIT_HRESP_ERR_EN (0x1 << 7)
#define BIT_RXFF_LEVEL (0x7 << 4)
#define BIT_TWO_8BIT_SENSOR (0x1 << 3)
#define BIT_ZERO_PACK_EN (0x1 << 2)
#define BIT_ECC_INT_EN (0x1 << 1)
#define BIT_ECC_AUTO_EN (0x1 << 0)
#define SHIFT_FRMCNT 16
/* csi status reg */
#define BIT_SFF_OR_INT (0x1 << 25)
#define BIT_RFF_OR_INT (0x1 << 24)
#define BIT_DMA_TSF_DONE_SFF (0x1 << 22)
#define BIT_STATFF_INT (0x1 << 21)
#define BIT_DMA_TSF_DONE_FB2 (0x1 << 20)
#define BIT_DMA_TSF_DONE_FB1 (0x1 << 19)
#define BIT_RXFF_INT (0x1 << 18)
#define BIT_EOF_INT (0x1 << 17)
#define BIT_SOF_INT (0x1 << 16)
#define BIT_F2_INT (0x1 << 15)
#define BIT_F1_INT (0x1 << 14)
#define BIT_COF_INT (0x1 << 13)
#define BIT_HRESP_ERR_INT (0x1 << 7)
#define BIT_ECC_INT (0x1 << 1)
#define BIT_DRDY (0x1 << 0)
#define CSI_MCLK_VF 1
#define CSI_MCLK_ENC 2