Commit 45edfa15 authored by Liu Ying's avatar Liu Ying Committed by Terry Lv

ENGR00221457 MX6DL clock:Set PLL3_PFD_540M to 540MHz

This patch sets PLL3_PFD_540M clock frequency to 540MHz
so that IPU and VPU clock can reach 270MHz.
Signed-off-by: default avatarLiu Ying <Ying.Liu@freescale.com>
(cherry picked from commit faf59e846f03b37c65996e58d045de8d64481283)
parent 4cc44ceb
......@@ -5412,6 +5412,8 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
/* on mx6dl gpu2d_axi_clk source from mmdc0 directly */
clk_set_parent(&gpu2d_axi_clk, &mmdc_ch0_axi_clk[0]);
clk_set_rate(&pll3_pfd_540M, 540000000);
clk_set_parent(&ipu1_clk, &pll3_pfd_540M);
/* pxp & epdc */
clk_set_parent(&ipu2_clk, &pll2_pfd_400M);
......
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