Commit 804a4d36 authored by Ranjani Vaidyanathan's avatar Ranjani Vaidyanathan

ENGR00221277 MX6DL/S - Set AXI clock to 270MHz

Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from  periph_clk just before the DDR
freq  is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Signed-off-by: default avatarRanjani Vaidyanathan <ra5478@freescale.com>
parent aece51a1
......@@ -109,6 +109,7 @@ static struct clk *pll1_sw_clk;
static struct clk *pll3_sw_clk;
static struct clk *pll2_200;
static struct clk *mmdc_ch0_axi;
static struct clk *pll3_540;
static struct delayed_work low_bus_freq_handler;
......@@ -126,6 +127,14 @@ static void reduce_bus_freq_handler(struct work_struct *work)
}
if (!cpu_is_mx6sl()) {
if (cpu_is_mx6dl() &&
(clk_get_parent(axi_clk) != periph_clk))
/* Set the axi_clk to be sourced from the periph_clk.
* So that its frequency can be lowered down to 50MHz
* or 24MHz as the case may be.
*/
clk_set_parent(axi_clk, periph_clk);
clk_enable(pll3);
if (lp_audio_freq) {
/* Need to ensure that PLL2_PFD_400M is kept ON. */
......@@ -302,6 +311,11 @@ int set_high_bus_freq(int high_bus_freq)
if (audio_bus_freq_mode)
clk_disable(pll2_400);
/* AXI_CLK is sourced from PLL3_PFD_540 on MX6DL */
if (cpu_is_mx6dl() &&
clk_get_parent(axi_clk) != pll3_540)
clk_set_parent(axi_clk, pll3_540);
low_bus_freq_mode = 0;
audio_bus_freq_mode = 0;
......@@ -538,6 +552,13 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
return PTR_ERR(pll3);
}
pll3_540 = clk_get(NULL, "pll3_pfd_540M");
if (IS_ERR(pll3_540)) {
printk(KERN_DEBUG "%s: failed to get periph_clk\n",
__func__);
return PTR_ERR(pll3_540);
}
pll3_sw_clk = clk_get(NULL, "pll3_sw_clk");
if (IS_ERR(pll3_sw_clk)) {
printk(KERN_DEBUG "%s: failed to get pll3_sw_clk\n",
......
......@@ -5409,14 +5409,15 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
/* pxp & epdc */
clk_set_parent(&ipu2_clk, &pll2_pfd_400M);
clk_set_rate(&ipu2_clk, 200000000);
clk_set_parent(&axi_clk, &pll3_pfd_540M);
} else if (cpu_is_mx6q()) {
clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]);
clk_set_rate(&gpu3d_core_clk[0], 528000000);
clk_set_parent(&ipu2_clk, &mmdc_ch0_axi_clk[0]);
clk_set_parent(&ipu1_clk, &mmdc_ch0_axi_clk[0]);
clk_set_parent(&axi_clk, &periph_clk);
}
clk_set_parent(&axi_clk, &periph_clk);
/* Need to keep PLL3_PFD_540M enabled until AXI is sourced from it. */
clk_enable(&axi_clk);
......
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