Commit b6606f03 authored by Gary Zhang's avatar Gary Zhang

ENGR00220027-1 IOMUX: add api for special pad bits configuration

Original pad configuration does not provide enough bitfield width
to config some bits, such as LVE bit and DDR_SEL bits.
like gpr configuration, add a api to implement these special
bits pad configuration, and user may call this api in board file.
Signed-off-by: default avatarGary Zhang <b13634@freescale.com>
parent 72b2444c
......@@ -2,6 +2,8 @@
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
* <armlinux@phytec.de>
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
......@@ -89,6 +91,11 @@ typedef u64 iomux_v3_cfg_t;
#define NO_PAD_I 0
#define NO_MUX_I 0
#ifdef CONFIG_SOC_IMX6Q
#define PAD_CTL_LVE (1 << 22)
#define PAD_CTL_LVE_MASK (1 << 22)
#define PAD_CTL_DDR_SEL_LPDDR2 (2 << 18)
#define PAD_CTL_DDR_SEL_DDR3 (3 << 18)
#define PAD_CTL_DDR_SEL_MASK (3 << 18)
#define PAD_CTL_HYS (1 << 16)
#define PAD_CTL_PUS_100K_DOWN (0 << 14)
......@@ -173,5 +180,11 @@ void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
* Set bits for general purpose registers
*/
void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value);
/*
* Set special bits for iomux registers, such as LVE bit, DDR_SEL bits
*/
void mxc_iomux_set_specialbits_register(u32 pad_addr, u32 value, u32 mask);
#endif /* __MACH_IOMUX_V3_H__*/
/*
* Copyright 2004-2011 Freescale Semiconductor, Inc.
* Copyright 2004-2012 Freescale Semiconductor, Inc.
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
* <armlinux@phytec.de>
......@@ -86,6 +86,15 @@ void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int valu
__raw_writel(reg, base + group * 4);
}
EXPORT_SYMBOL(mxc_iomux_set_gpr_register);
void mxc_iomux_set_specialbits_register(u32 pad_addr, u32 value, u32 mask)
{
u32 reg;
reg = __raw_readl(base + pad_addr);
reg &= ~mask;
reg |= value;
__raw_writel(reg, base + pad_addr);
}
EXPORT_SYMBOL(mxc_iomux_set_specialbits_register);
void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
{
......
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