ENGR00221161 [MX6SL]- Add audio bus freq mode support.
Set DDR to 50MHz in low power audio playback. AHB/AXI are at 24MHz. Also fix correct usecount for PLL1 main clock. If not it causes issues when pll1_sw_clk's parent is changed. Signed-off-by: Ranjani Vaidyanathan <firstname.lastname@example.org>
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