Commit d772cfee authored by Robby Cai's avatar Robby Cai

ENGR00220161: imx6sl: Add EVK board Support

- Copied the board file from ARM2, and consolidated the pinmux setting.
- Added a new pmic file for EVK.
- Added a new mach type.
- Added board_is_mx6sl_evk() API for late use if needed.
- Updated the defconfig
Signed-off-by: default avatarRobby Cai <R63905@freescale.com>
parent b0af671c
......@@ -311,6 +311,7 @@ CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y
CONFIG_MACH_MX6Q_ARM2=y
CONFIG_MACH_MX6SL_ARM2=y
CONFIG_MACH_MX6SL_EVK=y
# CONFIG_MACH_MX6Q_SABRELITE is not set
CONFIG_MACH_MX6Q_SABRESD=y
# CONFIG_MACH_MX6Q_SABREAUTO is not set
......@@ -1595,14 +1596,6 @@ CONFIG_VIDEO_CAPTURE_DRIVERS=y
# CONFIG_VIDEO_M52790 is not set
# CONFIG_VIDEO_VIVI is not set
# CONFIG_VIDEO_MXC_CAMERA is not set
# CONFIG_MXC_CAMERA_MICRON111 is not set
# CONFIG_MXC_CAMERA_OV2640 is not set
# CONFIG_MXC_CAMERA_OV3640 is not set
# CONFIG_MXC_CAMERA_OV5640 is not set
# CONFIG_MXC_CAMERA_OV8820_MIPI is not set
# CONFIG_MXC_CAMERA_OV5642 is not set
# CONFIG_MXC_TVIN_ADV7180 is not set
# CONFIG_MXC_IPU_DEVICE_QUEUE_SDC is not set
CONFIG_VIDEO_MXC_OUTPUT=y
CONFIG_VIDEO_MXC_IPU_OUTPUT=y
# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
......
......@@ -107,6 +107,43 @@ config MACH_MX6SL_ARM2
Include support for i.MX 6Sololite Armadillo2 platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX6SL_EVK
bool "Support i.MX 6SoloLite EVK platform"
select ARCH_MX6Q
select SOC_IMX6SL
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_DMA
select IMX_HAVE_PLATFORM_FEC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_VIV_GPU
select IMX_HAVE_PLATFORM_IMX_DVFS
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_FSL_OTG
select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP
select IMX_HAVE_PLATFORM_AHCI
select IMX_HAVE_PLATFORM_IMX_OCOTP
select IMX_HAVE_PLATFORM_IMX_VIIM
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_SNVS_RTC
select IMX_HAVE_PLATFORM_IMX_PM
select IMX_HAVE_PLATFORM_IMX_SPDIF
select IMX_HAVE_PLATFORM_PERFMON
select IMX_HAVE_PLATFORM_IMX_EPDC
select IMX_HAVE_PLATFORM_IMX_SPDC
select IMX_HAVE_PLATFORM_IMX_PXP
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_DCP
select IMX_HAVE_PLATFORM_RANDOM_RNGC
select ARCH_HAS_RNGC
help
Include support for i.MX 6Sololite EVK platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX6Q_SABRELITE
bool "Support i.MX 6Quad SABRE Lite platform"
select ARCH_MX6Q
......
......@@ -10,10 +10,11 @@ mx6_mmdc.o mx6_ddr_freq.o
obj-$(CONFIG_ARCH_MX6) += clock.o mx6_suspend.o clock_mx6sl.o
obj-$(CONFIG_MACH_MX6Q_ARM2) += board-mx6q_arm2.o
obj-$(CONFIG_MACH_MX6SL_ARM2) += board-mx6sl_arm2.o mx6sl_arm2_pmic_pfuze100.o
obj-$(CONFIG_MACH_MX6SL_EVK) += board-mx6sl_evk.o mx6sl_evk_pmic_pfuze100.o
obj-$(CONFIG_MACH_MX6Q_SABRELITE) += board-mx6q_sabrelite.o
obj-$(CONFIG_MACH_MX6Q_SABRESD) += board-mx6q_sabresd.o mx6q_sabresd_pmic_pfuze100.o
obj-$(CONFIG_MACH_MX6Q_SABREAUTO) += board-mx6q_sabreauto.o mx6q_sabreauto_pmic_pfuze100.o
obj-$(CONFIG_SMP) += plat_hotplug.o platsmp.o headsmp.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
obj-$(CONFIG_IMX_PCIE) += pcie.o
obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o
\ No newline at end of file
obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o
This diff is collapsed.
......@@ -16,11 +16,68 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef _BOARD_MX6SL_ARM2_H
#define _BOARD_MX6SL_ARM2_H
#ifndef _BOARD_MX6SL_COMMON_H
#define _BOARD_MX6SL_COMMON_H
#include <mach/iomux-mx6sl.h>
static iomux_v3_cfg_t mx6sl_arm2_pads[] = {
#define MX6_BRD_USBOTG1_PWR IMX_GPIO_NR(4, 0) /* KEY_COL4 */
#define MX6_BRD_USBOTG2_PWR IMX_GPIO_NR(4, 2) /* KEY_COL5 */
#define MX6_BRD_LCD_PWR_EN IMX_GPIO_NR(4, 3) /* KEY_ROW5 */
#define MX6_BRD_SD1_WP IMX_GPIO_NR(4, 6) /* KEY_COL7 */
#define MX6_BRD_SD1_CD IMX_GPIO_NR(4, 7) /* KEY_ROW7 */
#define MX6_BRD_ECSPI1_CS0 IMX_GPIO_NR(4, 11) /* ECSPI1_SS0 */
#define MX6_BRD_HEADPHONE_DET IMX_GPIO_NR(4, 19) /* FEC_RX_ER */
#define MX6_BRD_SD2_WP IMX_GPIO_NR(4, 29) /* SD2_DAT6 */
#define MX6_BRD_SD2_CD IMX_GPIO_NR(5, 0) /* SD2_DAT7 */
#define MX6_BRD_SD3_CD IMX_GPIO_NR(3, 22) /* REF_CLK_32K */
#define MX6_BRD_FEC_PWR_EN IMX_GPIO_NR(4, 21) /* FEC_TX_CLK */
/* EPDC GPIO pins */
#define MX6SL_BRD_EPDC_SDDO_0 IMX_GPIO_NR(1, 7)
#define MX6SL_BRD_EPDC_SDDO_1 IMX_GPIO_NR(1, 8)
#define MX6SL_BRD_EPDC_SDDO_2 IMX_GPIO_NR(1, 9)
#define MX6SL_BRD_EPDC_SDDO_3 IMX_GPIO_NR(1, 10)
#define MX6SL_BRD_EPDC_SDDO_4 IMX_GPIO_NR(1, 11)
#define MX6SL_BRD_EPDC_SDDO_5 IMX_GPIO_NR(1, 12)
#define MX6SL_BRD_EPDC_SDDO_6 IMX_GPIO_NR(1, 13)
#define MX6SL_BRD_EPDC_SDDO_7 IMX_GPIO_NR(1, 14)
#define MX6SL_BRD_EPDC_SDDO_8 IMX_GPIO_NR(1, 15)
#define MX6SL_BRD_EPDC_SDDO_9 IMX_GPIO_NR(1, 16)
#define MX6SL_BRD_EPDC_SDDO_10 IMX_GPIO_NR(1, 17)
#define MX6SL_BRD_EPDC_SDDO_11 IMX_GPIO_NR(1, 18)
#define MX6SL_BRD_EPDC_SDDO_12 IMX_GPIO_NR(1, 19)
#define MX6SL_BRD_EPDC_SDDO_13 IMX_GPIO_NR(1, 20)
#define MX6SL_BRD_EPDC_SDDO_14 IMX_GPIO_NR(1, 21)
#define MX6SL_BRD_EPDC_SDDO_15 IMX_GPIO_NR(1, 22)
#define MX6SL_BRD_EPDC_GDCLK IMX_GPIO_NR(1, 31)
#define MX6SL_BRD_EPDC_GDSP IMX_GPIO_NR(2, 2)
#define MX6SL_BRD_EPDC_GDOE IMX_GPIO_NR(2, 0)
#define MX6SL_BRD_EPDC_GDRL IMX_GPIO_NR(2, 1)
#define MX6SL_BRD_EPDC_SDCLK IMX_GPIO_NR(1, 23)
#define MX6SL_BRD_EPDC_SDOE IMX_GPIO_NR(1, 25)
#define MX6SL_BRD_EPDC_SDLE IMX_GPIO_NR(1, 24)
#define MX6SL_BRD_EPDC_SDSHR IMX_GPIO_NR(1, 26)
#define MX6SL_BRD_EPDC_PWRCOM IMX_GPIO_NR(2, 11)
#define MX6SL_BRD_EPDC_PWRSTAT IMX_GPIO_NR(2, 13)
#define MX6SL_BRD_EPDC_PWRCTRL0 IMX_GPIO_NR(2, 7)
#define MX6SL_BRD_EPDC_PWRCTRL1 IMX_GPIO_NR(2, 8)
#define MX6SL_BRD_EPDC_PWRCTRL2 IMX_GPIO_NR(2, 9)
#define MX6SL_BRD_EPDC_PWRCTRL3 IMX_GPIO_NR(2, 10)
#define MX6SL_BRD_EPDC_BDR0 IMX_GPIO_NR(2, 5)
#define MX6SL_BRD_EPDC_BDR1 IMX_GPIO_NR(2, 6)
#define MX6SL_BRD_EPDC_SDCE0 IMX_GPIO_NR(1, 27)
#define MX6SL_BRD_EPDC_SDCE1 IMX_GPIO_NR(1, 28)
#define MX6SL_BRD_EPDC_SDCE2 IMX_GPIO_NR(1, 29)
#define MX6SL_BRD_EPDC_SDCE3 IMX_GPIO_NR(1, 30)
#define MX6SL_BRD_EPDC_PMIC_WAKE IMX_GPIO_NR(2, 14) /* EPDC_PWRWAKEUP */
#define MX6SL_BRD_EPDC_PMIC_INT IMX_GPIO_NR(2, 12) /* EPDC_PWRINT */
#define MX6SL_BRD_EPDC_VCOM IMX_GPIO_NR(2, 3)
/* ELAN TS */
#define MX6SL_BRD_ELAN_CE IMX_GPIO_NR(2, 9)
#define MX6SL_BRD_ELAN_INT IMX_GPIO_NR(2, 10)
#define MX6SL_BRD_ELAN_RST IMX_GPIO_NR(4, 4)
static iomux_v3_cfg_t mx6sl_brd_pads[] = {
/* AUDMUX */
MX6SL_PAD_AUD_TXC__AUDMUX_AUD3_TXC,
......@@ -158,7 +215,7 @@ static iomux_v3_cfg_t mx6sl_arm2_pads[] = {
MX6SL_PAD_WDOG_B__WDOG1_WDOG_B,
};
static iomux_v3_cfg_t mx6sl_arm2_epdc_enable_pads[] = {
static iomux_v3_cfg_t mx6sl_brd_epdc_enable_pads[] = {
/* EPDC */
MX6SL_PAD_EPDC_D0__EPDC_SDDO_0,
MX6SL_PAD_EPDC_D1__EPDC_SDDO_1,
......@@ -197,7 +254,7 @@ static iomux_v3_cfg_t mx6sl_arm2_epdc_enable_pads[] = {
MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14,
};
static iomux_v3_cfg_t mx6sl_arm2_epdc_disable_pads[] = {
static iomux_v3_cfg_t mx6sl_brd_epdc_disable_pads[] = {
/* EPDC */
MX6SL_PAD_EPDC_D0__GPIO_1_7,
MX6SL_PAD_EPDC_D1__GPIO_1_8,
......@@ -236,7 +293,7 @@ static iomux_v3_cfg_t mx6sl_arm2_epdc_disable_pads[] = {
MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14,
};
static iomux_v3_cfg_t mx6sl_arm2_spdc_enable_pads[] = {
static iomux_v3_cfg_t mx6sl_brd_spdc_enable_pads[] = {
/* SPDC data*/
MX6SL_PAD_EPDC_D0__TCON_E_DATA_0,
MX6SL_PAD_EPDC_D1__TCON_E_DATA_1,
......@@ -280,7 +337,7 @@ static iomux_v3_cfg_t mx6sl_arm2_spdc_enable_pads[] = {
MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14,
};
static iomux_v3_cfg_t mx6sl_arm2_spdc_disable_pads[] = {
static iomux_v3_cfg_t mx6sl_brd_spdc_disable_pads[] = {
MX6SL_PAD_EPDC_D0__GPIO_1_7,
MX6SL_PAD_EPDC_D1__GPIO_1_8,
MX6SL_PAD_EPDC_D2__GPIO_1_9,
......@@ -315,7 +372,7 @@ static iomux_v3_cfg_t mx6sl_arm2_spdc_disable_pads[] = {
MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14,
};
static iomux_v3_cfg_t mx6sl_arm2_elan_pads[] = {
static iomux_v3_cfg_t mx6sl_brd_elan_pads[] = {
MX6SL_PAD_EPDC_PWRCTRL3__GPIO_2_10, /* INT */
MX6SL_PAD_EPDC_PWRCTRL2__GPIO_2_9, /* CE */
MX6SL_PAD_KEY_COL6__GPIO_4_4, /* RST */
......
This diff is collapsed.
This diff is collapsed.
......@@ -94,6 +94,8 @@ extern unsigned int system_rev;
board_is_rev(IMX_BOARD_REV_2))
#define board_is_mx6q_sabre_auto() (cpu_is_mx6q() && \
board_is_rev(IMX_BOARD_REV_3))
#define board_is_mx6sl_evk() (cpu_is_mx6sl() && \
board_is_rev(IMX_BOARD_REV_3))
#define board_is_mx6_unknown() \
board_is_rev(IMX_BOARD_REV_1)
......
......@@ -1118,4 +1118,5 @@ mx6q_sabrelite MACH_MX6Q_SABRELITE MX6Q_SABRELITE 3769
mx6q_sabresd MACH_MX6Q_SABRESD MX6Q_SABRESD 3980
mx6q_arm2 MACH_MX6Q_ARM2 MX6Q_ARM2 3837
mx6sl_arm2 MACH_MX6SL_ARM2 MX6SL_ARM2 4091
mx6sl_evk MACH_MX6SL_EVK MX6SL_EVK 4307
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