ENGR00220496 MX6SL:Add low power IDLE mode optimizations.
Add support for DDR freq change code in IRAM. Change PLL2 to bypass mode so that DDR is running off 24MHz OSC directly. ARM is now sourced from PLL1 (running at 800MHz) in this mode. This is required for the next step in IDLE mode optmization where all PLLs will be disabled when ARM enters WFI. Signed-off-by: Ranjani Vaidyanathan <firstname.lastname@example.org>
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