1. 16 Nov, 2012 2 commits
  2. 15 Nov, 2012 2 commits
    • make shi's avatar
      ENGR00233728 mx6 usb: change usb driver load from arch_initcall to module_init · 3042d8dc
      make shi authored
      We should use module_init as usb driver initialization entry point.
      To avoid the following crash when sabreauto board bootup:
      Unable to handle kernel NULL pointer dereference at virtual address 00000030
      pgd = 80004000
      [00000030] *pgd=00000000
      Internal error: Oops: 5 [#1] PREEMPT SMP
      Modules linked in:
      CPU: 0    Not tainted  (3.0.35-02249-g64936321-dirty #3070)
      PC is at gpio_set_value_cansleep+0x20/0x34
      LR is at mx6_usb_h1_init+0x68/0x188
      pc : [<80251638>]    lr : [<80010bd4>]    psr: 20000013
      sp : e4049f60  ip : 000000ef  fp : 00000000
      r10: 00000000  r9 : 00000000  r8 : e4049f8c
      r7 : 80521f04  r6 : e4049f80  r5 : 80521f10  r4 : 80af53cc
      r3 : 00000000  r2 : 00000001  r1 : 00000001  r0 : 00000000
      Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
      Control: 10c53c7d  Table: 1000404a  DAC: 00000015
      Process swapper (pid: 1, stack limit = 0xe40482f0)
      Stack: (0xe4049f60 to 0xe404a000)
      9f60: 80af53cc 80010bd4 00000001 02184200 0000004a 00000001 02184200 00000048
      9f80: 00000001 0000004d 0000004a 00000001 0000004d 00000048 8002e020 80af4ac0
      9fa0: 00000000 80010b6c 00000000 8003b4c4 00000000 80130000 00000000 80abf898
      9fc0: 000001f0 8002e020 8002e564 80042040 00000013 00000000 00000000 00000000
      9fe0: 00000000 800083cc 00000000 80008334 80042040 80042040 5104b14a f0e00000
      [<80251638>] (gpio_set_value_cansleep+0x20/0x34) from [<80010bd4>]
      (mx6_usb_h1_init+0x68/0x188)
      [<80010bd4>] (mx6_usb_h1_init+0x68/0x188) from [<8003b4c4>]
      (do_one_initcall+0x30/0x16c)
      [<8003b4c4>] (do_one_initcall+0x30/0x16c) from [<800083cc>]
      (kernel_init+0x98/0x144)
      [<800083cc>] (kernel_init+0x98/0x144) from [<80042040>]
      (kernel_thread_exit+0x0/0x8)
      Code: e92d4010 e7933100 e1a02001 e1a00003 (e5931030)
      ---[ end trace 1b75b31a2719ed1c ]---
      Kernel panic - not syncing: Attempted to kill init!
      [<8004823c>] (unwind_backtrace+0x0/0xfc) from [<8051d790>]
      (panic+0x74/0x19c)
      [<8051d790>] (panic+0x74/0x19c) from [<80078ba8>] (do_exit+0x664/0x718)
      [<80078ba8>] (do_exit+0x664/0x718) from [<80044fcc>] (die+0x250/0x2c8)
      [<80044fcc>] (die+0x250/0x2c8) from [<8004ba74>]
      (__do_kernel_fault+0x64/0x84)
      [<8004ba74>] (__do_kernel_fault+0x64/0x84) from [<8004bc14>]
      (do_page_fault+0x180/0x2e0)
      [<8004bc14>] (do_page_fault+0x180/0x2e0) from [<8003b400>]
      (do_DataAbort+0x34/0x98)
      [<8003b400>] (do_DataAbort+0x34/0x98) from [<80040f10>]
      (__dabt_svc+0x70/0xa0)
      
      Some board for example sabreauto board usb power gpio is use a io
      i2c expander gpio, gpio i2c driver load use subsys_initcall as driver
      initialization entry point, so gpio is not accessible at early bootup.
      Signed-off-by: default avatarmake shi <b15407@freescale.com>
      3042d8dc
    • Anson Huang's avatar
      ENGR00233732 mx6dl: change 996M setpoint voltage · 1ac50b59
      Anson Huang authored
      Change 996M setpoint voltage according to datasheet,
      lower VDDARM_CAP from 1.275V to 1.25V, and VDDSOC/PU_CAP
      from 1.275V to 1.175V.
      Signed-off-by: default avatarAnson Huang <b20788@freescale.com>
      1ac50b59
  3. 14 Nov, 2012 3 commits
  4. 13 Nov, 2012 1 commit
  5. 09 Nov, 2012 1 commit
    • Fugang Duan's avatar
      ENGR00224109 - MX6 : FEC : optimize ENET_REF_CLK PAD configuration. · 5722518f
      Fugang Duan authored
      In MX6 Arik and Rigel platforms, RGMII tx_clk clock source is from
      ENET_REF_CLK pad supplied by phy. To optimize the clk signal path,
      the ENET_REF_CLK I/O must have this configuration:
      	1. Disable on-chip pull-up, pull-down, and keeper
      	2. Disable hysteresis
      	3. Speed = 100 MHz
      	4. Slew rate = fast
      
      The optimizition make the bias point match the optimum point, which
      can maximize design margin.
      Signed-off-by: default avatarFugang Duan  <B38611@freescale.com>
      5722518f
  6. 07 Nov, 2012 1 commit
  7. 06 Nov, 2012 2 commits
  8. 05 Nov, 2012 3 commits
  9. 02 Nov, 2012 1 commit
    • Xinyu Chen's avatar
      ENGR00231826 imx esdhc: Add the DMA mask for esdhc device register. · a0cf2469
      Xinyu Chen authored
      We must set the DMA mask for esdhc device.
      To avoid the following crash when we do not have highmem pages:
      
      [<c0044f90>] (__dabt_svc+0x70/0xa0) from [<c00cf460>]
      [<c00cf460>] (mempool_alloc+0x3c/0x108) from [<c00f4aa4>]
      [<c00f4aa4>] (blk_queue_bounce+0xc0/0x2fc) from [<c023761c>]
      [<c023761c>] (__make_request+0x20/0x2b8) from [<c0235bb4>]
      [<c0235bb4>] (generic_make_request+0x3b4/0x4cc) from [<c0235d74>]
      [<c0235d74>] (submit_bio+0xa8/0x128) from [<c01279c4>]
      [<c01279c4>] (submit_bh+0x108/0x178) from [<c012baa0>]
      [<c012baa0>] (block_read_full_pag+e0x278/0x394) from [<c00cd520>]
      [<c00cd520>] (do_read_cache_page+0x70/0x154) from [<c00cd64c>]
      [<c00cd64c>] (read_cache_page_async+0x1c/0x24) from [<c00cd65c>]
      [<c00cd65c>] (read_cache_page+0x8/0x10) from [<c014c354>]
      [<c014c354>] (read_dev_sector+0x30/0x68) from [<c014dd4c>]
      [<c014dd4c>] (read_lba+0xa0/0x164) from [<c014e300>]
      [<c014e300>] (efi_partition+0x9c/0xed4) from [<c014ca0c>]
      [<c014ca0c>] (rescan_partitions+0x15c/0x480) from [<c012f190>]
      [<c012f190>] (__blkdev_get+0x324/0x394) from [<c012f300>]
      [<c012f300>] (blkdev_get+0x100/0x358) from [<c023e5f4>]
      [<c023e5f4>] (register_disk+0x140/0x164) from [<c023e73c>]
      [<c023e73c>] (add_disk+0x124/0x2a0) from [<c03a7528>]
      [<c03a7528>] (mmc_add_disk+0x10/0x68) from [<c03a7820>]
      [<c03a7820>] (mmc_blk_probe+0x15c/0x20c) from [<c039cc90>]
      [<c039cc90>] (mmc_bus_probe+0x18/0x1c) from [<c0294e28>]
      
      When our DDR size is small or reserved memory are large and
      the lowmem can cover all the available pages for kernel,
      the highmem pages will not be setup. That means the page_pool
      for bounce queue can not be create in init_emergency_pool().
      And page_pool will stay NULL without initialized.
      In the mmc/card/queue.c the blk_queue_bounce_limit()
      function will be called in mmc_init_queue() to
      initialize the request_queue and it's bounce_gfp.
      If we do not define the DMA mask for our platform,
      then the BLK_BOUNCE_HIGH (lowmem pfn) will be set
      as limit to queue bounce, which means the blk_queue_bounce
      will use page_pool to iterate over the bio segment.
      Under the circumstances that highmem is not setup,
      the page_pool is null, and causes kernel crash.
      After set the DMA mask for esdhci device, the page_pool
      will not be used to iterate over the bio segment.
      Signed-off-by: default avatarXinyu Chen <xinyu.chen@freescale.com>
      a0cf2469
  10. 01 Nov, 2012 1 commit
  11. 31 Oct, 2012 1 commit
    • Robin Gong's avatar
      ENGR00231910 PU regulator: do not disable PU regulator · d2cd924f
      Robin Gong authored
      If system enter suspend/resume during VPU encoding on Rigel, there will be
      "VPU blocking: timeout." error . But there is ok if enter suspend/resume
      during VPU decoding and enter suspend/resume during encoding/decoding  on
      Arik, until now we didn't know the root cause, so revert it firstly.
      Because the previous patch about PU regulator is composed with four commits
      and hard to revert, now we adopt simplest way that do not disable PU regulator
      in low level. The negative impact is there will several mA increasment in
      suspend, we will fix it ASAP.
      Signed-off-by: default avatarRobin Gong <b38343@freescale.com>
      d2cd924f
  12. 29 Oct, 2012 5 commits
  13. 26 Oct, 2012 3 commits
  14. 25 Oct, 2012 1 commit
    • make shi's avatar
      ENGR00230167 MX6 regulator: enable and raise the voltage of USB 3p0 LDO · 2e671ab5
      make shi authored
      The USB FS eye test will fail in MX6 board if the 3V USB phy LDO is not enabled.
      Setting enable bit (bit-0) of LDO 3p0 will make 3p0 LDO to use bandgap output as
      reference voltage, LDO output will be accurate. And HW team suggest that it is
      better to raise the voltage of USB 3p0 phy LDO 3.2V to pass the USB compliance
      testing.
      
      - Implement vdd3p0 regulator enable and disable function to support
        enable and disable the LDO 3p0 regulator.
      - Use regulator API to enable the USB 3p0 phy LDO and raise the LDO
        to 3.2V during system boot up. And disable the LDO before system
        enter suspend and enable the LDO again after system resume.
      Signed-off-by: default avatarmake shi <b15407@freescale.com>
      2e671ab5
  15. 23 Oct, 2012 2 commits
  16. 19 Oct, 2012 3 commits
  17. 17 Oct, 2012 1 commit
  18. 16 Oct, 2012 2 commits
    • Ranjani Vaidyanathan's avatar
      ENGR00229924 MX6SL-Fix MMDC FIFO reset code. · bff791a2
      Ranjani Vaidyanathan authored
      Write to the MMDC registers when resetting the MMDC after the
      DDR I/Os have been floated.
      
      This fixes the bug introduced by the commit:
      "2a2f65bd
      MX6SL-Reset MMDC read FIFO in low power IDLE"
      Signed-off-by: default avatarRanjani Vaidyanathan <ra5478@freescale.com>
      bff791a2
    • Ranjani Vaidyanathan's avatar
      ENGR00229695 MX6x-Set RBC counters correctly in STOP mode. · 23e5dd7b
      Ranjani Vaidyanathan authored
      The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
      block is sending signals to power gate the core. This is apart
      from the RBC counter's basic functionality to act as counter to
      power down the analog portions of the chip.
      But the counter needs to be set/cleared only when no interrupts
      are pending. And also for correct hold off the interrupts, enable the
      counter as close to WFI as possible.
      The RBC counts CKIL cycles (32KHz)
      So follow the following steps to set the counter
      in suspend/resume in mx6_suspend.S:
      1. Mask all the GPC interrupts.
      2. Write the counter value to the RBC
      3. Enable the RBC
      4. Unmask all the interrupts.
      5. Busy wait for a few usecs to wait for RBC to start counting
      in case an interrupt is pending.
      4. Execute WFI
      Reset the counter after resume in pm.c:
      1. Mask all the GPC interrupts.
      2. Disable the counter.
      3. Set the RBC counter to 0.
      4. Wait for 80usec for the write to get accepted.
      5. Unmask all the interrupts.
      
      With the above steps, we can minimize the PDNSCR and PUPSCR counters
      in the GPC. The basic condition for the RBC counter:
      RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
      PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
      PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)
      Signed-off-by: default avatarRanjani Vaidyanathan <ra5478@freescale.com>
      23e5dd7b
  19. 15 Oct, 2012 2 commits
  20. 14 Oct, 2012 1 commit
  21. 13 Oct, 2012 1 commit
  22. 12 Oct, 2012 1 commit