1. 16 Nov, 2012 1 commit
    • Terry Lv's avatar
      ENGR00233929: add kernel command line to enable snvs · 11f3fa3d
      Terry Lv authored
      In MX6Q/DL, originally GPIO_0 is used as CKO pin function. when SNVS
      module is enabled, CKO output stops suddenly.
      Both CKO clock config register CCOSR and GPIO_0 IOMUX register value are
      not changed. But because ALT7 of GPIO_0 pad is SNVS_VIO_5 function. I
      doubt that when SNVS module is enabled, GPIO_0 pad is automatically
      changed to SNVS instance by SoC.
      Thus we add option for snvs enable/disable.
      Signed-off-by: default avatarTerry Lv <r65388@freescale.com>
      11f3fa3d
  2. 15 Nov, 2012 2 commits
    • make shi's avatar
      ENGR00233728 mx6 usb: change usb driver load from arch_initcall to module_init · 3042d8dc
      make shi authored
      We should use module_init as usb driver initialization entry point.
      To avoid the following crash when sabreauto board bootup:
      Unable to handle kernel NULL pointer dereference at virtual address 00000030
      pgd = 80004000
      [00000030] *pgd=00000000
      Internal error: Oops: 5 [#1] PREEMPT SMP
      Modules linked in:
      CPU: 0    Not tainted  (3.0.35-02249-g64936321-dirty #3070)
      PC is at gpio_set_value_cansleep+0x20/0x34
      LR is at mx6_usb_h1_init+0x68/0x188
      pc : [<80251638>]    lr : [<80010bd4>]    psr: 20000013
      sp : e4049f60  ip : 000000ef  fp : 00000000
      r10: 00000000  r9 : 00000000  r8 : e4049f8c
      r7 : 80521f04  r6 : e4049f80  r5 : 80521f10  r4 : 80af53cc
      r3 : 00000000  r2 : 00000001  r1 : 00000001  r0 : 00000000
      Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
      Control: 10c53c7d  Table: 1000404a  DAC: 00000015
      Process swapper (pid: 1, stack limit = 0xe40482f0)
      Stack: (0xe4049f60 to 0xe404a000)
      9f60: 80af53cc 80010bd4 00000001 02184200 0000004a 00000001 02184200 00000048
      9f80: 00000001 0000004d 0000004a 00000001 0000004d 00000048 8002e020 80af4ac0
      9fa0: 00000000 80010b6c 00000000 8003b4c4 00000000 80130000 00000000 80abf898
      9fc0: 000001f0 8002e020 8002e564 80042040 00000013 00000000 00000000 00000000
      9fe0: 00000000 800083cc 00000000 80008334 80042040 80042040 5104b14a f0e00000
      [<80251638>] (gpio_set_value_cansleep+0x20/0x34) from [<80010bd4>]
      (mx6_usb_h1_init+0x68/0x188)
      [<80010bd4>] (mx6_usb_h1_init+0x68/0x188) from [<8003b4c4>]
      (do_one_initcall+0x30/0x16c)
      [<8003b4c4>] (do_one_initcall+0x30/0x16c) from [<800083cc>]
      (kernel_init+0x98/0x144)
      [<800083cc>] (kernel_init+0x98/0x144) from [<80042040>]
      (kernel_thread_exit+0x0/0x8)
      Code: e92d4010 e7933100 e1a02001 e1a00003 (e5931030)
      ---[ end trace 1b75b31a2719ed1c ]---
      Kernel panic - not syncing: Attempted to kill init!
      [<8004823c>] (unwind_backtrace+0x0/0xfc) from [<8051d790>]
      (panic+0x74/0x19c)
      [<8051d790>] (panic+0x74/0x19c) from [<80078ba8>] (do_exit+0x664/0x718)
      [<80078ba8>] (do_exit+0x664/0x718) from [<80044fcc>] (die+0x250/0x2c8)
      [<80044fcc>] (die+0x250/0x2c8) from [<8004ba74>]
      (__do_kernel_fault+0x64/0x84)
      [<8004ba74>] (__do_kernel_fault+0x64/0x84) from [<8004bc14>]
      (do_page_fault+0x180/0x2e0)
      [<8004bc14>] (do_page_fault+0x180/0x2e0) from [<8003b400>]
      (do_DataAbort+0x34/0x98)
      [<8003b400>] (do_DataAbort+0x34/0x98) from [<80040f10>]
      (__dabt_svc+0x70/0xa0)
      
      Some board for example sabreauto board usb power gpio is use a io
      i2c expander gpio, gpio i2c driver load use subsys_initcall as driver
      initialization entry point, so gpio is not accessible at early bootup.
      Signed-off-by: default avatarmake shi <b15407@freescale.com>
      3042d8dc
    • Anson Huang's avatar
      ENGR00233732 mx6dl: change 996M setpoint voltage · 1ac50b59
      Anson Huang authored
      Change 996M setpoint voltage according to datasheet,
      lower VDDARM_CAP from 1.275V to 1.25V, and VDDSOC/PU_CAP
      from 1.275V to 1.175V.
      Signed-off-by: default avatarAnson Huang <b20788@freescale.com>
      1ac50b59
  3. 14 Nov, 2012 3 commits
  4. 07 Nov, 2012 1 commit
  5. 06 Nov, 2012 1 commit
  6. 05 Nov, 2012 3 commits
  7. 01 Nov, 2012 1 commit
  8. 31 Oct, 2012 1 commit
    • Robin Gong's avatar
      ENGR00231910 PU regulator: do not disable PU regulator · d2cd924f
      Robin Gong authored
      If system enter suspend/resume during VPU encoding on Rigel, there will be
      "VPU blocking: timeout." error . But there is ok if enter suspend/resume
      during VPU decoding and enter suspend/resume during encoding/decoding  on
      Arik, until now we didn't know the root cause, so revert it firstly.
      Because the previous patch about PU regulator is composed with four commits
      and hard to revert, now we adopt simplest way that do not disable PU regulator
      in low level. The negative impact is there will several mA increasment in
      suspend, we will fix it ASAP.
      Signed-off-by: default avatarRobin Gong <b38343@freescale.com>
      d2cd924f
  9. 29 Oct, 2012 2 commits
  10. 26 Oct, 2012 2 commits
  11. 25 Oct, 2012 1 commit
    • make shi's avatar
      ENGR00230167 MX6 regulator: enable and raise the voltage of USB 3p0 LDO · 2e671ab5
      make shi authored
      The USB FS eye test will fail in MX6 board if the 3V USB phy LDO is not enabled.
      Setting enable bit (bit-0) of LDO 3p0 will make 3p0 LDO to use bandgap output as
      reference voltage, LDO output will be accurate. And HW team suggest that it is
      better to raise the voltage of USB 3p0 phy LDO 3.2V to pass the USB compliance
      testing.
      
      - Implement vdd3p0 regulator enable and disable function to support
        enable and disable the LDO 3p0 regulator.
      - Use regulator API to enable the USB 3p0 phy LDO and raise the LDO
        to 3.2V during system boot up. And disable the LDO before system
        enter suspend and enable the LDO again after system resume.
      Signed-off-by: default avatarmake shi <b15407@freescale.com>
      2e671ab5
  12. 23 Oct, 2012 1 commit
  13. 19 Oct, 2012 3 commits
  14. 17 Oct, 2012 1 commit
  15. 16 Oct, 2012 2 commits
    • Ranjani Vaidyanathan's avatar
      ENGR00229924 MX6SL-Fix MMDC FIFO reset code. · bff791a2
      Ranjani Vaidyanathan authored
      Write to the MMDC registers when resetting the MMDC after the
      DDR I/Os have been floated.
      
      This fixes the bug introduced by the commit:
      "2a2f65bd
      MX6SL-Reset MMDC read FIFO in low power IDLE"
      Signed-off-by: default avatarRanjani Vaidyanathan <ra5478@freescale.com>
      bff791a2
    • Ranjani Vaidyanathan's avatar
      ENGR00229695 MX6x-Set RBC counters correctly in STOP mode. · 23e5dd7b
      Ranjani Vaidyanathan authored
      The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
      block is sending signals to power gate the core. This is apart
      from the RBC counter's basic functionality to act as counter to
      power down the analog portions of the chip.
      But the counter needs to be set/cleared only when no interrupts
      are pending. And also for correct hold off the interrupts, enable the
      counter as close to WFI as possible.
      The RBC counts CKIL cycles (32KHz)
      So follow the following steps to set the counter
      in suspend/resume in mx6_suspend.S:
      1. Mask all the GPC interrupts.
      2. Write the counter value to the RBC
      3. Enable the RBC
      4. Unmask all the interrupts.
      5. Busy wait for a few usecs to wait for RBC to start counting
      in case an interrupt is pending.
      4. Execute WFI
      Reset the counter after resume in pm.c:
      1. Mask all the GPC interrupts.
      2. Disable the counter.
      3. Set the RBC counter to 0.
      4. Wait for 80usec for the write to get accepted.
      5. Unmask all the interrupts.
      
      With the above steps, we can minimize the PDNSCR and PUPSCR counters
      in the GPC. The basic condition for the RBC counter:
      RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
      PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
      PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)
      Signed-off-by: default avatarRanjani Vaidyanathan <ra5478@freescale.com>
      23e5dd7b
  16. 15 Oct, 2012 2 commits
  17. 13 Oct, 2012 1 commit
  18. 12 Oct, 2012 2 commits
  19. 09 Oct, 2012 4 commits
  20. 08 Oct, 2012 3 commits
    • Robert Lee's avatar
      ENGR00225700: ARM: mx6sl: Fix suspend/resume lockup · 8fa739fd
      Robert Lee authored
      Currently, the sequence and functionality we use to enter and exit
      suspend causes us to hang upon resuming.  It appears that this is being
      caused by two things.  The first is the powering off of the 2p5 rail
      which powers the IO pullups and  pulldowns.  The DQS pins were
      configured as pull downs.  The second is switching the DQS pins from
      differential to CMOS mode (and back).  This second problem only
      occurs on a few EVK boards.
      
      It is believed that these changes are causing glitches on the mmdc DQS
      pins which is putting garbage in the FIFO (or causing some other FIFO
      problem).  This patch adds two mmdc0 FIFO resets after exiting the
      suspend.  Two are thought to be needed per previous FIFO reset
      experience by Mike Kjar.
      
      Since the MMDC0 FIFO will be cleaned each time, we can now remove
      the code that configured the DQS lines as pull downs as we no
      longer care if they float.
      Signed-off-by: default avatarRobert Lee <robert.lee@freescale.com>
      8fa739fd
    • Robert Lee's avatar
      ENGR00227422: ARM: imx6sl: Adjust ARM and SOC stby voltages · 75bd68f1
      Robert Lee authored
      According to the latest specification data, these rails should
      go no lower than 900mV in standby mode.  This patch modifies
      the existing mx6sl board files and sets the pmic standby voltage
      for these rails to be 925mV (extra 25mV to account for pmic accuracy).
      Signed-off-by: default avatarRobert Lee <robert.lee@freescale.com>
      75bd68f1
    • Ranjani Vaidyanathan's avatar
      ENGR00227426 MX6SL-Fix bugs in low power IDLE mode · 13eafe65
      Ranjani Vaidyanathan authored
      Need to ensure that DDR IO pads are not floated when
      a peripheral that needs DDR is active, for ex SDMA.
      Also need to keep IPMUX clock enabled even when ARM
      is in WFI, so set the CCGR bits accordingly.
      Signed-off-by: default avatarRanjani Vaidyanathan <ra5478@freescale.com>
      13eafe65
  21. 09 Oct, 2012 2 commits
  22. 08 Oct, 2012 1 commit