support adjust VDDSOC if enable LDO bypass on mx6_sabresd board
Signed-off-by: Robin Gong <B38343@freescale.com>

Add port speed define MACRO to arc_otg.h.
Signed-off-by: make shi <b15407@freescale.com>

For i.MX6DLTO1.1 and i.MX6DQTO1.2, the disconnection-bit can only be set after
the resume finished, otherwise, the remote-wake-up may fail. Because if the
device not switch to High-Speed 45ohm termination resistors mode, when the
disconnection  detection bit is set the disconnection detection circuit will
detect a high speed disconnection by mistake.
Signed-off-by: make shi <b15407@freescale.com>

We can't modify the usecount of pfd 400M clock when ARM freq
is changed, as when the children of pfd 400M do clock enable/disable,
they will also modify this usecount, these two modification is
out of same lock protection. And this wrong usecount may lead to
pfd 400M or pll2 disabled accidently, and it will cause system hang!
Signed-off-by: Anson Huang <b20788@freescale.com>

1. Adjust ARM/SOC/PU voltage according to latest datasheet;
2. Remove Rigel's 200M setpoint to align with Arik.
Signed-off-by: Anson Huang <b20788@freescale.com>

The function has been implement in LDO enable , but not in LDO bypass.
Implement it on mx6sl.
Signed-off-by: Robin Gong <B38343@freescale.com>

This patch sets PLL3_PFD_540M clock frequency to 540MHz
so that IPU and VPU clock can reach 270MHz.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit faf59e846f03b37c65996e58d045de8d64481283)

Set DDR to 50MHz in low power audio playback.
AHB/AXI are at 24MHz.
Also fix correct usecount for PLL1 main clock. If not
it causes issues when pll1_sw_clk's parent is changed.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

Checking of the bus_freq variables and changing of the
bus/ddr frequency should be done under one mutex.
Else there is a race-condition that the variable changed
just after it was checked.
Also ensure that the bus freq is always increased before
the cpu freq is set to anything other than the lowest setpoint.
Else there is a possibility that the ARM is set to run from
PLL1 at higher frequency when bus/DDR are still at 24MHz.
This is dangerous since when system enters WAIT mode in
low bus freq state, PLL1 is set to bypass when ARM is being
sourced from it.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

Add a new working point table to MX6SL and set the voltages
according to the latest datasheet.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

Add platform device for V4L2 support
Signed-off-by: Robby Cai <R63905@freescale.com>

The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1
is off. So we should keep the 1V1 active during the system suspend if any USB
host enabled.
- Add stop_mode_config to 1 with refcount
- Add mutex to protect the refcount and HW_ANADIG_ANA_MISC0 register
- If stop_mode_config is set as 1, the otg  vbus wakeup system will be supported
Signed-off-by: make shi <b15407@freescale.com>

MSL headfile part change.
Signed-off-by: make shi <b15407@freescale.com>

Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from  periph_clk just before the DDR
freq  is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

[MX6X] Fix BogoMIPS value is not correct
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>

mma8450q on E-INK DC3 boards, with i2c address 0x1c on I2C1.
Signed-off-by: Robby Cai <R63905@freescale.com>

config audio pads to avoid pop-noise
Signed-off-by: Gary Zhang <b13634@freescale.com>

Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled.
Signed-off-by: Robin Gong <B38343@freescale.com>

[MX6SL]MMDC: DDR Controller's measure unit may return an incorrect
value when operating below 100 MHz
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>

When ARM enters WFI in low power IDLE state, float the DDR
IO pins to drop the power on the VDDHIGH rail.
Need to run WFI code from IRAM since DDR needs to be
put into self-refresh before changing the IO pins.
Drop AHB to 8MHz and DDR to 1MHz when ARM is in WFI when
in IDLE state.
Set IPG_PERCLK to run at 3MHz, since we want to maintain a
1:2.5 ratio between PERCLK to AHB_CLK.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

ECSPI pin MX6DL_PAD_EIM_D17__ECSPI1_MISO is configured overlap by epdc
MX6DL_PAD_EIM_D17__GPIO_3_17, so that SPI-NOR flash can't work normally.
From schematic of ARM2 board, epdc and spi share this pin if plug epdc
daughter board. But SPI-NOR is on ARM2 mother board, so it should be config
well firstly. So we make sure SPI-NOR work successfully by default. But if
enable epdc , SPI-NOR on ARM2 will work fail.
Signed-off-by: Robin Gong <B38343@freescale.com>

- Set MX6SL_PAD_HSIC_DAT and MX6SL_PAD_HSIC_STROBE pad DDR attribute as DDR3
- Add imx6sl_add_fsl_ehci_hs and imx6sl_add_fsl_usb2_hs_wakeup in usb_h2.c
Signed-off-by: make shi <b15407@freescale.com>

1. BUS freq's set low bus setpoint using delat work, which
didn't have mutex lock, so in some scenarios, set high bus
freq function can be called at the same time, we need to move
mutex lock into these two routine;

2. Using pm notify to make sure bus freq set to high setpoint
before supend and restore after resume.

3. Clear build warning.
Signed-off-by: Anson Huang <b20788@freescale.com>

In order to support USB remote wake up, we should keep the PLL3 enable
and power bit all the time. We use BM_ANADIG_ANA_MISC2_CONTROL0 to control
the PLL3 power off PLL3's power when PLL3 is not used by other module.

PLL3 power design logic as below:
usb1_pll_480_ctrl_power_int=hw_anadig_usb1_pll_480_ctrl_power && ((disable_480_p
ll_n && ~hw_anadig_ana_misc2_control0 )||pwrctl_otg_wakeup || utmi_otg_suspendm)
There are two basic case:
- If USB is active and USB remote wakeup happen , Pll3 will be turn on.
- If USB is not active and no remote wakeup happen, the PLL3 will be controlled
  by hw_anadig_ana_misc2_control0 bit.
Signed-off-by: make shi <b15407@freescale.com>

The ENABLE bit is not set for all PLLs by default. Ensure
that the pll_enable() function sets this bit for all PLLs.
The pll_disable() function should not clear this bit
for PLL1, PLL2, PLL3 and PLL7. The output of these PLLs
maybe used even if they are bypassed.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

The problem is caused because the board init routine don't add the
corresponding device node. Problem resolved after add them
Signed-off-by: Eric Sun <jian.sun@freescale.com>

The problem is caused because "mx6_sabrelite_board_init" don't add the
corresponding device node. Problem resolved after add them.
Signed-off-by: Eric Sun <jian.sun@freescale.com>

Fix build break due to missing extern.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

Add support for DDR freq change code in IRAM.
Change PLL2 to bypass mode so that DDR is running off 24MHz OSC
directly.
ARM is now sourced from PLL1 (running at 800MHz) in this mode.
This is required for the next step in IDLE mode optmization
where all PLLs will be disabled when ARM enters WFI.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

for avoiding pop-noise adn setting audmux pad to 1.8v on evk,
add pad ctrl for audmux iomux setting
Signed-off-by: Gary Zhang <b13634@freescale.com>

Original pad configuration does not provide enough bitfield width
to config some bits, such as LVE bit and DDR_SEL bits.
like gpr configuration, add a api to implement these special
bits pad configuration, and user may call this api in board file.
Signed-off-by: Gary Zhang <b13634@freescale.com>

pdata->lowpower may be accessed at two drivers together, assumed
the situation that host/device set phy to low power mode but
still not set the flag lowpower, at this time the wakeup occurs, as
the flag lowpower is still not set, the interrupt will be infinite loop
as no one will serve it.

This commit is for MSL code and add protect at wakeup interrupt.
Signed-off-by: Peter Chen <peter.chen@freescale.com>

Keep the corresponding rail of pfuze: VGEN4 and VGEN1 "always on".
It's required for any IO pad configured as this voltage.
It has to be always on, even in DSM mode.
Signed-off-by: Robby Cai <R63905@freescale.com>

Adjust pfuse settings for wm8962
Signed-off-by: Gary Zhang <b13634@freescale.com>

SOC/PU voltage need to following some rules according to latest
datasheet:

1. SOC/PU CAP voltage must be 1.15V <= SOC/PU <= 1.3V;
2. SOC and PU must be same as they don't have level shift;
3. Adjust previous wrong voltage setting.

If SOC/PU voltage is too low, may cause system crash on some
chips, we have a board that easily crash with GPU working and
doing some tar operation, with this voltage adjust, this issue
fixed.
Signed-off-by: Anson Huang <b20788@freescale.com>

Fix not able to set high bus frequency from low bus frequency.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>

This patch sets CABC_EN0/1 to low to disable LVDS panel
CABC function so that LVDS backlight will not be turned
by the LVDS panel automatically so that we may avoid
annoying unstable backlight issue.
Signed-off-by: Rong Dian <b38775@freescale.com>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit a169940fb39216e644018304e3a3bdaca61ea88a)

This patch configures NANDF_CS2/3 to be GPIO_6_15/16 to
support LVDS CABC_EN0/1.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit fdff66991738a56a7e1bc735cf452d57f1771c13)

- Copied the board file from ARM2, and consolidated the pinmux setting.
- Added a new pmic file for EVK.
- Added a new mach type.
- Added board_is_mx6sl_evk() API for late use if needed.
- Updated the defconfig
Signed-off-by: Robby Cai <R63905@freescale.com>

When android doing suspend/resume, we may meet the issue of
backlight is not on (pwm pin no signal) after system wakeup.
The root cause is PWM sample can not be set into the PWMSAR
register after pwm being used and disabled for a while.
The value read back after write is 0 when this issue happens.

Do a software reset after pwm disable can resolve this
issue, this makes sure the next sample update is correct.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>