1. 29 Aug, 2012 4 commits
  2. 28 Aug, 2012 1 commit
  3. 27 Aug, 2012 1 commit
  4. 26 Aug, 2012 3 commits
  5. 24 Aug, 2012 5 commits
  6. 23 Aug, 2012 2 commits
  7. 22 Aug, 2012 2 commits
  8. 21 Aug, 2012 4 commits
    • Robin Gong's avatar
      ENGR00220776 mx6dl_arm2: ECSPI pin config overlaped by epdc · 11fc35eb
      Robin Gong authored
      ECSPI pin MX6DL_PAD_EIM_D17__ECSPI1_MISO is configured overlap by epdc
      MX6DL_PAD_EIM_D17__GPIO_3_17, so that SPI-NOR flash can't work normally.
      From schematic of ARM2 board, epdc and spi share this pin if plug epdc
      daughter board. But SPI-NOR is on ARM2 mother board, so it should be config
      well firstly. So we make sure SPI-NOR work successfully by default. But if
      enable epdc , SPI-NOR on ARM2 will work fail.
      Signed-off-by: default avatarRobin Gong <B38343@freescale.com>
    • make shi's avatar
      ENGR00220833 mx6sl: USB hsic: enable mx6sl hsic function · d0a87109
      make shi authored
      - Set MX6SL_PAD_HSIC_DAT and MX6SL_PAD_HSIC_STROBE pad DDR attribute as DDR3
      - Add imx6sl_add_fsl_ehci_hs and imx6sl_add_fsl_usb2_hs_wakeup in usb_h2.c
      Signed-off-by: default avatarmake shi <b15407@freescale.com>
    • Anson Huang's avatar
      ENGR00220370 [MX6]Fix BUS freq suspend/resume fail in low bus mode · 74474dc3
      Anson Huang authored
      1. BUS freq's set low bus setpoint using delat work, which
      didn't have mutex lock, so in some scenarios, set high bus
      freq function can be called at the same time, we need to move
      mutex lock into these two routine;
      2. Using pm notify to make sure bus freq set to high setpoint
      before supend and restore after resume.
      3. Clear build warning.
      Signed-off-by: default avatarAnson Huang <b20788@freescale.com>
    • make shi's avatar
      ENGR00218789 mx6: clock: keep PLL3 enable and power bit all the time · 30b0b3d6
      make shi authored
      In order to support USB remote wake up, we should keep the PLL3 enable
      and power bit all the time. We use BM_ANADIG_ANA_MISC2_CONTROL0 to control
      the PLL3 power off PLL3's power when PLL3 is not used by other module.
      PLL3 power design logic as below:
      usb1_pll_480_ctrl_power_int=hw_anadig_usb1_pll_480_ctrl_power && ((disable_480_p
      ll_n && ~hw_anadig_ana_misc2_control0 )||pwrctl_otg_wakeup || utmi_otg_suspendm)
      There are two basic case:
      - If USB is active and USB remote wakeup happen , Pll3 will be turn on.
      - If USB is not active and no remote wakeup happen, the PLL3 will be controlled
        by hw_anadig_ana_misc2_control0 bit.
      Signed-off-by: default avatarmake shi <b15407@freescale.com>
  9. 20 Aug, 2012 3 commits
  10. 19 Aug, 2012 1 commit
  11. 17 Aug, 2012 2 commits
  12. 16 Aug, 2012 6 commits
  13. 15 Aug, 2012 3 commits
  14. 14 Aug, 2012 3 commits