support adjust VDDSOC if enable LDO bypass on mx6_sabresd board
Signed-off-by: Robin Gong <B38343@freescale.com>

1. BUS freq's set low bus setpoint using delat work, which
didn't have mutex lock, so in some scenarios, set high bus
freq function can be called at the same time, we need to move
mutex lock into these two routine;

2. Using pm notify to make sure bus freq set to high setpoint
before supend and restore after resume.

3. Clear build warning.
Signed-off-by: Anson Huang <b20788@freescale.com>

This patch sets CABC_EN0/1 to low to disable LVDS panel
CABC function so that LVDS backlight will not be turned
by the LVDS panel automatically so that we may avoid
annoying unstable backlight issue.
Signed-off-by: Rong Dian <b38775@freescale.com>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit a169940fb39216e644018304e3a3bdaca61ea88a)

Add a 1ms debounce to the gpio key to avoid
unexpected gpio status read from gpio_key driver's
workqueue. This issue happens on android's resume stage,
sometimes the framework get more than one up key even
user press the power key once.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>

1.add new cpu setpoint: replace 498Mhz with 672Mhz,and remove 198Mhz.
  but now 498Mhz seems not stable enough, comment now, test enough to
  add it. Rigel kept unchange now.
2.support adjusting VDDSOC/VDDPU when cpu frequency change.
Signed-off-by: Robin Gong <b38343@freescale.com>

Replace mx6q_version() check with hdmi_SDMA_check() to add support
for HDMI_SDMA in RIGEL TO1.1.
Signed-off-by: Chen Liangjun <b36089@freescale.com>

For the latest B4 sabresd board, GPIO_1 is connected to PRO_B, we
use this pin as battery charge_done led control, need to avoid using
this pin as GPIO for B4 board, or system will reboot when this pin's
level is changed.
Signed-off-by: Anson Huang <b20788@freescale.com>

If MX6q chip version is bigger than TO1.2, Select HDMI SDMA
request as SDMA event 2 for MX6Q ARM2 board. SDMA event 2 can be
configured HDMI or IPU.
Signed-off-by: Chen Liangjun <b36089@freescale.com>

In MFG tool will use "flash_eraseall /dev/mtd0" command to erase whole mtd0
partition, but u-boot environment params are stored  in offset 0xc0000 which
exceed the u-boot patition 0x40000, it means the "flash_eraseall" command only
erase u-boot partition, but not environment area. So we need increase the size
of u-boot partition  to 0x100000 as what we remain 1MB for u-boot.
Signed-off-by: Robin Gong <B38343@freescale.com>

- remove mx6_usb_h1_init() in board specific initialization files
- Add module_init(mx6_usb_h1_init) and module_exit(mx6_usb_h1_exit) in usb_h1.c
  to support the usb_h1 modulization
- Export necessary function which is used in usb_h1.c
Signed-off-by: make shi <b15407@freescale.com>

This patch adds 2ms sleep after camera power down signal
is set to high or to low to ensure power down or up
is successful. OV5640/OV5642 camera specs say that they
require this condtion to be true - for PWDN to go low,
power must first become stable(DVDD to PWDN>=1ms), so
this patch simply use 2ms which should be enough.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>

Remove call memblock_free after reserve memory with memblock_allocate().
The function of memblock_free is to remove the memory block from reserve list
of memblock, it will totally lost the info about how much phy memory
we have.

Skipping call this can make the reserved memory be accountable in
memblock With no side-effect.

After doing this, we can know how much our phy memory is, then can add check
in our driver like(vpu) to check the phy memory valid or not before vpu start
use the address.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>

This patch refines OV csi camera reset sequence according to
OV's recommendation:
reset --------------------|_____|----------------
                        ->| 1ms |<-
pwdn  ----------|_________________________|------
              ->|   5ms   |<- ->|   5ms   |<-
    ->|   5ms   |<-
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit b4d3898a01c232b2525637fa1bb443f8b6208d0e)

This patch refines OV mipi camera reset sequence according to
OV's recommendation:
reset --------------------|_____|----------------
                        ->| 1ms |<-
pwdn  ----------|_________________________|------
              ->|   5ms   |<- ->|   5ms   |<-
    ->|   5ms   |<-

This change makes the OV mipi camera be at a correct status
after reset, otherwise, the wrong status of OV mipi camera
will reduce the ~2.78V analog camera power to ~2.3V, which
causes random thin colorful lines on OV5642 CSI camera image
as OV5642 CSI camera uses the same analog power.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 9e78895d8856651b769908e63d4ebc514314eeaa)

Fix perfmon:no mxs-perfmon.0 directory after inserting mxs-perfmon.ko.
Signed-off-by: Frank Li <Frank.Li@freescale.com>

Added enable_pins/disable_pins functions for Mx6q/dl sabresd HDMI.
Added HDMI DDC IOMUX setting.
Signed-off-by: Sandor Yu <R01008@freescale.com>

Enable caam ahash feature in config.
Add caam init to other 6q platforms.
Signed-off-by: Terry Lv <r65388@freescale.com>

This patch corrects camera mclk and audio mclk frequency
to be 24MHz to align with 24MHz osc clock.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 00ea48ba38940c3a908f9a5d2e72ae285a221329)

On MX6 SabreSD board, gpio_0 is muxed to clko to be
audio mclk and camera mclk. 24MHz osc clk is a stable
clock source, which can meet the requirement of audio
mclk and camera mclk. This patch sets clko parent
clock to be clko2 clock so that camera mclk and audio
mclk can source from osc clk.
There are 2 benifits after applying this patch:
1) clko's original parent clock(pll4_audio_main_clk)
can be gated off to save power or used by another
module.
2) ov5640/ov5642 camera most settings can reach
claimed 15fps or 30fps with no human eye recognizable
video quality downgrade.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit ace3723ceff0d546e0176f74ad38d58a6d11b7ee)

* enable PCIe on ARD boards
* Configure the DEEM parameters to pass PCIe GEN2 stress tests
Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com>

Register PMU resources during system bootup, so that "Perf" Command can
be used to get misc performance data of a running program

The "Perf" Exe should be built manually in
"./tools/perf" using the following command line
> make CROSS_COMPILER=... ARCH=arm CFLAGS="-static -DGElf_Nhdr=Elf32_Nhdr"
then copy the "Perf" executable to rootfs/bin

Usage :
perf            # show help content
perf list       # show all available statistics options
perf stat ls    # show all statistics of a "ls" command
perf stat -e cycles tar cvfz bin.tgz /bin
                # show "cycles" statistics of command
                #     "tar cvfz ...."

MX6 Series Chips bound all CPUs PERFMON IRQ to one, this may cause some
problems when get per-CPU statistics. Need further investigation
Signed-off-by: Eric Sun <jian.sun@freescale.com>

The default .config defines the GPU as a module:
  "CONFIG_MXC_GPU_VIV=m"

In this case, we actually can not find the CONFIG_MXC_GPU_VIV.
We should find CONFIG_MXC_GPU_VIV_MODULE instead.
Signed-off-by: Huang Shijie <b32955@freescale.com>

If miss to configure IRQ for max11801, the max11801 driver fails to
probe and returns error,sabresd battery driver also fails to sample
voltage by max11801 ADC.
Signed-off-by: Rong Dian <b38775@freescale.com>

operate WM8962 MCLK by callback
Signed-off-by: Gary Zhang <b13634@freescale.com>

dual camera support for mx6q and mx6dl:
1. let mipi and parallel camera working on different csi
2. the two camera can work independently and synchronously
3. the two camera will be registered and different video
   device(/dev/video0, /dev/video1)
4. when both camera are working, the can not use the same
   ipu channel, that is, when camera one using PRP_ENC_MEM
   or PRP_VF_MEM channel, the other one can only use CSI_MEM

   this is the arch part changes.
Signed-off-by: Wu Guoxing <b39297@freescale.com>

To avoid the ARM from accepting an interrupt in the dangerous
window, reduce the ARM core freq just before the sytem is
about to enter WAIT state.
Reduce the ARM freq so as to maintain 12:5 ARM_CLK to IPG
ratio. Use the ARM_PODF to drop the frequency.
In a multicore case the frequency is dropped only when all the
4 cores are going to be in WFI.

In case of single core environment, its easy to drop the ARM core
freq just before WFI since there is no need to identify the state of
the other cores.

Some other points to note:
1. If "mem_clk_on" is added to the command line, the memory clocks will
not be gated in WAIT mode. This will increase the system IDLE power.
This mode is valid only on MX6sl, MX6DQ TO1.2 and MX6DL TO1.1.
2. In case the IPG clk is too low (for ex 50MHz) and ARM is at 1GHz,
we cannot match the 12:5 ratio using ARM_PODF only. In this case,
donot clock gate the memories in WAIT mode (available on MX6SL,
MXDQ TO1.2 and MXDL TO1.1). For MXDQ TO1.1 and MX6DL TO1.0, disable
system wide WAIT entry in this case.

In STOP mode, always ensure that the memory clocks are gated, else
power impact will be significant.

WAIT mode is enabled by default with this commit.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

1.add MMC_PM_WAKE_SDIO_IRQ capability, it should be
used together with MMC_PM_KEEP_POWER although not support
SDIO wakeup in function.
2.add MMC_CAP_NONREMOVABLE to describe imx6's three sdhc
devices's removable feature.Now emmc is permanent,sdio and
sd is removable instead of all default were permanent before.
According to this feature, detimine whether reinit card
or not in resume.
Signed-off-by: B38613 <B38613@freescale.com>

The current code will reserve 128M for GPU even when it is not enabled.

It is not needed. So do not reserve the memory when the GPU is not enabled.
(this can save 128M for Mfgtool.)
Signed-off-by: Huang Shijie <b32955@freescale.com>

Add PCIE 3V3 power up/down routing if we do not have
pcie driver selected. And power up 3V3 in board init.
As the reset function of the hw board cannot reset the
modem power. So on kernel boot up, we must make sure
the 3g modem is reset correctly by gpio reset.
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>

The LVDS display direction should be aligned with camera sensor.
So we rotate it with 180 degree.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>

VDDCORE output directly from pfuze not internal anatop regulator,VDDCORE can
be adjust by pfuze regulator with deifferent cpu frequency, these patch should
be used with u-boot related patch, because LDO bypass is set on u-boot. u-boot
and kernel can be configured by CONFIG_MX6_INTER_LDO_BYPASS, by default it is
disabled, can be used on RevC. These code is put in arch/arm.
Signed-off-by: Robin Gong <B38343@freescale.com>

move max8903 interrupt pin config from board-mx6q_sabresd.c into
sabresd_battery driver on SABRESD_rev.B board.
Signed-off-by: Rong Dian <b38775@freescale.com>

Add enable_lcd_ldb command line option for dual display
with LVDS and WVGA LCD panel together on MX6DL.
Signed-off-by: Wayne Zou <b36644@freescale.com>

Since the ldb clock source is different from mipi display,
it doesn't need this option.
Signed-off-by: Wayne Zou <b36644@freescale.com>

Configure PINMUX for max8903 driver on SABRESD_rev.B board.
Signed-off-by: Rong Dian <b38775@freescale.com>

Configure PINMUX for ELAN driver on MX6DL SABRESD
Signed-off-by: Robby Cai <R63905@freescale.com>

Add led-gpio control and trigger for sabresd
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>

Configure PINMUX for max11801 driver on SABRESD_rev.B board.
Signed-off-by: Rong Dian <b38775@freescale.com>

Add support for scaling the bus frequency (both DDR
and ahb_clk).
The DDR and AHB_CLK are dropped to 24MHz when all devices
that need high AHB frequency are disabled and the CORE
frequency is at the lowest setpoint.
The DDR is dropped to 400MHz for the video playback usecase.
In this mode the GPU, FEC, SATA etc are disabled.

To scale the bus frequency, its necessary that all cores
except the core that is executing the DDR frequency change
are in WFE. This is achieved by generating interrupts on
un-used interrupts (Int no 139, 144, 145 and 146).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

    When system is going to enter WAIT mode, set PLL1 to 24MHz
    so that ARM is running at 24MHz. This is a SW workaround for
    the WAIT mode issue.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>