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  1. 22 Aug, 2012 7 commits
    • Nancy Chen's avatar
      ENGR00220989 [MX6SL]: DDR Controller measure unit workaround · d25abd9d
      Nancy Chen authored 
      [MX6SL]MMDC: DDR Controller's measure unit may return an incorrect
value when operating below 100 MHz
Signed-off-by: default avatarNancy Chen <Nancy.Chen@freescale.com>
      d25abd9d
    • Sandor Yu's avatar
      ENGR00220538 HDMI: Clock mismatch in suspend&resume when video playback · 2a1c7b7e
      Sandor Yu authored 
      In suspend/resume and HDMI plugin/plugout stress test,
sometimes fbcon will call fb_set_par with
parameter fb_var_screeninfo that xres anfd yres is zero.
MX frame buffer driver can not correct handle this casue,
it will cause IPU pixel clock gating/ungating mismatch.

Check fb_var_screeninfo parameter in mxcfb_check_var and
mxcfb_set_par function, returned if xres,yres zero.
Signed-off-by: default avatarSandor Yu <R01008@freescale.com>
      2a1c7b7e
    • Ranjani Vaidyanathan's avatar
      ENGR00220696 [MX6SL]-Reduce IDLE mode power consumption. · 3348f4fc
      Ranjani Vaidyanathan authored 
      When ARM enters WFI in low power IDLE state, float the DDR
IO pins to drop the power on the VDDHIGH rail.
Need to run WFI code from IRAM since DDR needs to be
put into self-refresh before changing the IO pins.
Drop AHB to 8MHz and DDR to 1MHz when ARM is in WFI when
in IDLE state.
Set IPG_PERCLK to run at 3MHz, since we want to maintain a
1:2.5 ratio between PERCLK to AHB_CLK.
Signed-off-by: default avatarRanjani Vaidyanathan <ra5478@freescale.com>
      3348f4fc
    • Wayne Zou's avatar
      ENGR00221012 IPU: Clean up dead code · 5d309473
      Wayne Zou authored 
      IPU: Clean up dead code
Signed-off-by: default avatarWayne Zou <b36644@freescale.com>
      5d309473
    • Ryan QIAN's avatar
      ENGR00219601-02: mmc: sdhci: revise pre_req & post_req to improve performance · 16f59122
      Ryan QIAN authored 
      Test Env:
1. MX6DL SabreSD board.
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52MHz.
3. Test commands:
  3.1 Writing command:
  # dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
  3.2 Reading command:
  # echo 1 > /proc/sys/vm/drop_caches
  # echo 1 > /proc/sys/vm/drop_caches
  # sleep 1
  # dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100

Performance result with this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) |    ADMA     |
|----------+--------------+-------------+-------------|
|   1Ghz   |  ~11MB/s (w) | ~5MB/s (w)  | ~11MB/s (w) |
|          |  ~25MB/s (r) | ~25MB/s (r) | ~23MB/s (r) |
|----------+--------------+-------------+-------------|
|  200Mhz  |  ~8MB/s (w)  | ~5MB/s (w)  | ~9MB/s (w)  |
|          |  ~16MB/s (r) | ~20MB/s (r) | ~13MB/s (r) |
-------------------------------------------------------

Performance result without this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) |    ADMA     |
|----------+--------------+-------------+-------------|
|   1Ghz   |  ~10MB/s (w) | ~5MB/s (w)  | ~10MB/s (w) |
|          |  ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
|  200Mhz  |  ~8MB/s (w)  | ~4MB/s (w)  | ~8MB/s (w)  |
|          |  ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: default avatarRyan QIAN <b32804@freescale.com>
      16f59122
    • Ryan QIAN's avatar
      ENGR00219601-01: mmc: queue: enlarge the size of bounce buffer for SDMA. · 834211af
      Ryan QIAN authored 
      - set bounce buffer to 512KB from 64K, which is hw max seg size for
fsl sd host controller
- by enlarging the size of bounce buffer, it will reduce the number
of irq on writing by merging small requests into a large one, which
will improve writing throughput.
- the side effect is that the reading throughput of 512KB bounce buffer
is lower than the one of 64KB bounce buffer, when cpu freq is at 200Mhz.

Test Env:
1. MX6DL SabreSD board
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52Mhz
3. Test commands:
  3.1 Writing test command:
  # dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
  3.2 Reading test command:
  # echo 1 > /proc/sys/vm/drop_caches
  # echo 1 > /proc/sys/vm/drop_caches
  # sleep 1
  # dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100

Performance result:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) |    ADMA     |
|----------+--------------+-------------+-------------|
|   1Ghz   |  ~10MB/s (w) | ~5MB/s (w)  | ~10MB/s (w) |
|          |  ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
|  200Mhz  |  ~8MB/s (w)  | ~4MB/s (w)  | ~8MB/s (w)  |
|          |  ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: default avatarRyan QIAN <b32804@freescale.com>
      834211af
    • Liu Ying's avatar
      ENGR00220734 IPUv3 fb:Rewind eof irq sync mechanism back · 7e8bcd60
      Liu Ying authored 
      This patch changes to use original sync mechanism for eof
irq, which may improve pan-display or alpha buffer update
performance.
1) Initialize flip_completion and alpha_flip_completion
only once when fb is initialized instead of initializing
it every time when pan display is called.
2) Clear and enable eof irq after selecting buffer ready.
In this way, we have no chance to lose an interrupt, as
selecting a new buffer ready doesn't make the eof irq
come(from the newly selected buffer) before we clear the irq
status and enable the irq. Otherwise, if we clear the irq
status and enable the irq before we doing down in pan-display
or alpha buffer update, we have chance(users call pan-display or
alpha buffer update faster than vsync frequency and blocks at
down()) to clear an unhandled irq, which may cause performance
issue.
Signed-off-by: default avatarLiu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 67c2bd5edef363412a074e9b4130b5207dac8a7f)
      7e8bcd60
  3. 21 Aug, 2012 9 commits
  5. 20 Aug, 2012 5 commits
  7. 19 Aug, 2012 1 commit
  9. 18 Aug, 2012 2 commits
  11. 17 Aug, 2012 8 commits
  13. 16 Aug, 2012 8 commits