1. 28 Jan, 2016 1 commit
    • Michael Schanz's avatar
      CGT000028 QMX6: remove revision check of EXT CSD · 6fc1ccd2
      Michael Schanz authored
      Revision checking of EXT CSD area avoids that new eMMC devices are recognized
      at all. In the past, it has been observed that new types are still backward
      compatible and handled correctly, although not supported with complete feature set.
      This patch removes the revision checking of the EXT CSD area in order to get
      the driver working for devices with EXT_CSD rev. 6 and above.
      Signed-off-by: Michael Schanz's avatarMichael Schanz <michael.schanz@congatec.com>
      6fc1ccd2
  2. 28 Oct, 2015 1 commit
    • Michael Schanz's avatar
      CGT000027 QMX6: adjust camera rst signal/Q7 GPIO1 for · 79771165
      Michael Schanz authored
       conga-QMX6 hardware revision C.x
      
      In Q7 Spec. 2.0, the USB_OTG_PWR signal was moved from Q7 Connector, Pin 186 to Pin 56.
      Moreover the connector layout of the MIPI connector was specified.
      
      conga-QMX6 rev. C.x was designed according the new Q7 Spec. 2.0 (& Errata). In order to
      fulfill this requirement, this patch was released to adjust the device tree configuration.
      
      In detail, this patch
      - remaps the camera reset signal from GPIO1_8 (R5) to GPIO6_5 (L6). This frees GPIO1_8
      in order to be used as Q7 GPIO1 (Pin 186).
      
      - removes signal GPIO3_22 from the device tree configuration. In previous hardware
      revisions (e.g. A.x, B.x), this signal was used as Q7 GPIO1 (Pin 186).
      
      Attention: this patch breaks compatibility with rev. B.x boards when Q7 GPIO1 is in use.
      Signed-off-by: Michael Schanz's avatarMichael Schanz <michael.schanz@congatec.com>
      79771165
  3. 09 Oct, 2015 1 commit
  4. 08 Oct, 2015 2 commits
  5. 19 Feb, 2015 5 commits
  6. 06 Feb, 2015 3 commits
  7. 04 Feb, 2015 1 commit
  8. 16 Jan, 2015 1 commit
  9. 15 Jan, 2015 1 commit
  10. 03 Dec, 2014 11 commits
  11. 24 Oct, 2014 1 commit
  12. 23 Oct, 2014 1 commit
  13. 14 Oct, 2014 1 commit
  14. 13 Oct, 2014 2 commits
  15. 09 Oct, 2014 1 commit
  16. 29 Sep, 2014 1 commit
    • Shawn Guo's avatar
      ARM: imx: fix .is_enabled() of shared gate clock · 920fa48d
      Shawn Guo authored
      Commit 63288b721a80 ("ARM: imx: fix shared gate clock") attempted to fix
      an issue with particular enable/disable sequence from two shared gate
      clocks.  But unfortunately, while it partially fixed the issue, it also
      did something wrong in .is_enabled() function hook.  In case of shared
      gate, the function shouldn't really query the hardware state via
      share_count, because the function is trying to query the enabling state
      of the clock in question, not the hardware state which is shared by
      multiple clocks.
      
      Fix the issue by returning the enable_count of the clock itself which is
      maintained by clock core, in case it's a clock sharing hardware gate
      with others.  As the result, the initialization of share_count per
      hardware state is not needed now.  So remove it.
      
      shawn.guo: cherry-pick commit 9e1ac462b982 from upstream
      Reported-by: 's avatarFabio Estevam <fabio.estevam@freescale.com>
      Fixes: 63288b721a80 ("ARM: imx: fix shared gate clock")
      Cc: <stable@vger.kernel.org>
      Signed-off-by: 's avatarShawn Guo <shawn.guo@freescale.com>
      Tested-by: 's avatarFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: 's avatarOlof Johansson <olof@lixom.net>
      920fa48d
  17. 25 Sep, 2014 2 commits
  18. 07 Aug, 2014 1 commit
  19. 06 Aug, 2014 3 commits
    • Dong Aisheng's avatar
      ENGR00324668 mmc: core: add delay for SD3.0 UHS mode switch · ef3bce5f
      Dong Aisheng authored
      We may meet the following errors with a SD3.0 DDR50 cards during reboot test.
      mmc0: new ultra high speed DDR50 SDHC card at address aaaa
      mmcblk0: mmc0:aaaa SU08G 7.40 GiB
      mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00
      mmcblk0: retrying using single block read
      mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0
      end_request: I/O error, dev mmcblk0, sector 0
      .....
      Buffer I/O error on device mmcblk0, logical block 0
       mmcblk0: unable to read partition table
      
      The root cause is still unknown.
      Since there's an errata of Sandisk eMMC card before that it requires delay for CMD6
      for eMMC DDR mode to work stable, we also suspect the SD3.0 DDR requires similar delay.
      (Still not confirmed by Sandisk)
      By adding the delay, the overnight reboot test(run 2000+ times) did not
      show the issue anymore. Originally it can easy show the error after about 20 times of
      reboot test.
      
      So this patch would be the temporary workaround for Sandisk SD3.0 DDR50 mode
      unstable issue.
      Signed-off-by: 's avatarDong Aisheng <b29396@freescale.com>
      ef3bce5f
    • Xianzhong's avatar
      ENGR00325794 [#1087] fix video memory mutex sharing issue · 789d6703
      Xianzhong authored
      the root cause is video memory mutex is not global variable,
      it will cause video memory managment problem with mixed 2D/3D/VG.
      
      kernel panic with multiple instances stress test running glesx_viv.sh.
      
      Date: Jul 31, 2014
      Signed-off-by: 's avatarXianzhong <b07117@freescale.com>
      Acked-by: Jason Liu
      (cherry picked from commit 9cec1cbd7ca2378e5c429f57d088d23d73d9c2f3)
      789d6703
    • Richard Zhu's avatar
      ENGR00325494 pcie:delay is requried after clks_en · c8a6b97f
      Richard Zhu authored
      - the async reset input need ref clock to sync internally,
      when the ref clock comes after reset, internal synced reset
      time is too short , cannot meet the requirement
      so, ssp_en should be asserted at least 4us after ref clock stable.
      - align to the community imx pcie driver, add the about
      200us delay to make sure that it can allow the pcie clks
      stabilize, when pcie clks are enabled on imx6q/dl/solo.
      Signed-off-by: 's avatarRichard Zhu <r65037@freescale.com>
      (cherry picked from commit 5d9635c8d92b21bc12753517fa3e9884417b19be)
      c8a6b97f