Commit b9b5306e authored by Khem Raj's avatar Khem Raj Committed by Koen Kooi

gcc-4.6: Bring in latest linaro patches

Adjust existing patches for latest FSF gcc-4_6-branch
Signed-off-by: default avatarKhem Raj <raj.khem@gmail.com>
Acked-by: default avatarMartin Jansa <Martin.Jansa@gmail.com>
Signed-off-by: default avatarKoen Kooi <koen@dominion.thruhere.net>
parent 9f2e5548
......@@ -17,8 +17,10 @@
for STORE_FLAG_VALUE==-1 case.
=== modified file 'gcc/combine.c'
--- old/gcc/combine.c 2011-02-15 19:46:26 +0000
+++ new/gcc/combine.c 2011-04-26 17:03:58 +0000
Index: gcc-4_6-branch/gcc/combine.c
===================================================================
--- gcc-4_6-branch.orig/gcc/combine.c 2011-09-16 19:58:21.000000000 -0700
+++ gcc-4_6-branch/gcc/combine.c 2011-09-16 20:05:36.626650681 -0700
@@ -391,8 +391,8 @@
static void undo_all (void);
static void undo_commit (void);
......@@ -30,7 +32,7 @@
static rtx simplify_if_then_else (rtx);
static rtx simplify_set (rtx);
static rtx simplify_logical (rtx);
@@ -3086,12 +3086,12 @@
@@ -3112,12 +3112,12 @@
if (i1)
{
subst_low_luid = DF_INSN_LUID (i1);
......@@ -45,7 +47,7 @@
}
}
@@ -3103,7 +3103,7 @@
@@ -3129,7 +3129,7 @@
self-referential RTL when we will be substituting I1SRC for I1DEST
later. Likewise if I0 feeds into I2, either directly or indirectly
through I1, and I0DEST is in I0SRC. */
......@@ -54,7 +56,7 @@
(i1_feeds_i2_n && i1dest_in_i1src)
|| ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
&& i0dest_in_i0src));
@@ -3142,7 +3142,7 @@
@@ -3168,7 +3168,7 @@
copy of I1SRC each time we substitute it, in order to avoid creating
self-referential RTL when we will be substituting I0SRC for I0DEST
later. */
......@@ -63,7 +65,7 @@
i0_feeds_i1_n && i0dest_in_i0src);
substed_i1 = 1;
@@ -3172,7 +3172,7 @@
@@ -3198,7 +3198,7 @@
n_occurrences = 0;
subst_low_luid = DF_INSN_LUID (i0);
......@@ -72,7 +74,7 @@
substed_i0 = 1;
}
@@ -3234,7 +3234,7 @@
@@ -3260,7 +3260,7 @@
{
rtx t = i1pat;
if (i0_feeds_i1_n)
......@@ -81,7 +83,7 @@
XVECEXP (newpat, 0, --total_sets) = t;
}
@@ -3242,10 +3242,10 @@
@@ -3268,10 +3268,10 @@
{
rtx t = i2pat;
if (i1_feeds_i2_n)
......@@ -94,7 +96,7 @@
XVECEXP (newpat, 0, --total_sets) = t;
}
@@ -4914,11 +4914,13 @@
@@ -4943,11 +4943,13 @@
IN_DEST is nonzero if we are processing the SET_DEST of a SET.
......@@ -109,7 +111,7 @@
{
enum rtx_code code = GET_CODE (x);
enum machine_mode op0_mode = VOIDmode;
@@ -4979,7 +4981,7 @@
@@ -5008,7 +5010,7 @@
&& GET_CODE (XVECEXP (x, 0, 0)) == SET
&& GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
{
......@@ -118,7 +120,7 @@
/* If this substitution failed, this whole thing fails. */
if (GET_CODE (new_rtx) == CLOBBER
@@ -4996,7 +4998,7 @@
@@ -5025,7 +5027,7 @@
&& GET_CODE (dest) != CC0
&& GET_CODE (dest) != PC)
{
......@@ -127,7 +129,7 @@
/* If this substitution failed, this whole thing fails. */
if (GET_CODE (new_rtx) == CLOBBER
@@ -5042,8 +5044,8 @@
@@ -5071,8 +5073,8 @@
}
else
{
......@@ -138,7 +140,7 @@
/* If this substitution failed, this whole thing
fails. */
@@ -5120,7 +5122,9 @@
@@ -5149,7 +5151,9 @@
&& (code == SUBREG || code == STRICT_LOW_PART
|| code == ZERO_EXTRACT))
|| code == SET)
......@@ -149,7 +151,7 @@
/* If we found that we will have to reject this combination,
indicate that by returning the CLOBBER ourselves, rather than
@@ -5177,7 +5181,7 @@
@@ -5206,7 +5210,7 @@
/* If X is sufficiently simple, don't bother trying to do anything
with it. */
if (code != CONST_INT && code != REG && code != CLOBBER)
......@@ -158,7 +160,7 @@
if (GET_CODE (x) == code)
break;
@@ -5197,10 +5201,12 @@
@@ -5226,10 +5230,12 @@
expression.
OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
......@@ -173,7 +175,7 @@
{
enum rtx_code code = GET_CODE (x);
enum machine_mode mode = GET_MODE (x);
@@ -5255,8 +5261,8 @@
@@ -5284,8 +5290,8 @@
false arms to store-flag values. Be careful to use copy_rtx
here since true_rtx or false_rtx might share RTL with x as a
result of the if_then_else_cond call above. */
......@@ -184,16 +186,16 @@
/* If true_rtx and false_rtx are not general_operands, an if_then_else
is unlikely to be simpler. */
@@ -5600,7 +5606,7 @@
@@ -5629,7 +5635,7 @@
{
/* Try to simplify the expression further. */
rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
- temp = combine_simplify_rtx (tor, mode, in_dest);
+ temp = combine_simplify_rtx (tor, mode, in_dest, 0);
- temp = combine_simplify_rtx (tor, VOIDmode, in_dest);
+ temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
/* If we could, great. If not, do not go ahead with the IOR
replacement, since PLUS appears in many special purpose
@@ -5693,7 +5699,16 @@
@@ -5722,7 +5728,16 @@
ZERO_EXTRACT is indeed appropriate, it will be placed back by
the call to make_compound_operation in the SET case. */
......@@ -211,7 +213,7 @@
&& new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
&& op1 == const0_rtx
&& mode == GET_MODE (op0)
@@ -5739,7 +5754,10 @@
@@ -5768,7 +5783,10 @@
/* If STORE_FLAG_VALUE is -1, we have cases similar to
those above. */
......@@ -223,7 +225,7 @@
&& new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
&& op1 == const0_rtx
&& (num_sign_bit_copies (op0, mode)
@@ -5937,11 +5955,11 @@
@@ -5966,11 +5984,11 @@
if (reg_mentioned_p (from, true_rtx))
true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
from, true_val),
......@@ -237,7 +239,7 @@
SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
@@ -6158,11 +6176,11 @@
@@ -6187,11 +6205,11 @@
{
temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
cond_op0, cond_op1),
......@@ -251,4 +253,3 @@
temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
if (extend_op != UNKNOWN)
2011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
Backport from mainline.
LP 791327
gcc/
2011-06-09 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
PR target/49335
* config/arm/predicates.md (add_operator): New.
* config/arm/arm.md ("*arith_shiftsi"): Fix for SP reg usage
in Thumb2.
2011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
Backport from mainline.
......@@ -19,69 +7,10 @@
PR target/49385
* config/arm/thumb2.md (*thumb2_movhi_insn): Make sure atleast
one of the operands is a register.
=== modified file 'gcc/config/arm/arm.md'
--- old/gcc/config/arm/arm.md 2011-06-27 22:14:07 +0000
+++ new/gcc/config/arm/arm.md 2011-06-28 12:02:27 +0000
@@ -8584,18 +8584,22 @@
;; Patterns to allow combination of arithmetic, cond code and shifts
(define_insn "*arith_shiftsi"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
- [(match_operand:SI 4 "s_register_operand" "r,r")
- (match_operand:SI 5 "shift_amount_operand" "M,r")])
- (match_operand:SI 2 "s_register_operand" "rk,rk")]))]
+ [(match_operand:SI 4 "s_register_operand" "r,r,r,r")
+ (match_operand:SI 5 "shift_amount_operand" "M,M,M,r")])
+ (match_operand:SI 2 "s_register_operand" "rk,rk,r,rk")]))]
"TARGET_32BIT"
"%i1%?\\t%0, %2, %4%S3"
[(set_attr "predicable" "yes")
(set_attr "shift" "4")
- (set_attr "arch" "32,a")
- ;; We have to make sure to disable the second alternative if
+ (set_attr "arch" "a,t2,t2,a")
+ ;; Thumb2 doesn't allow the stack pointer to be used for
+ ;; operand1 for all operations other than add and sub. In this case
+ ;; the minus operation is a candidate for an rsub and hence needs
+ ;; to be disabled.
+ ;; We have to make sure to disable the fourth alternative if
;; the shift_operator is MULT, since otherwise the insn will
;; also match a multiply_accumulate pattern and validate_change
;; will allow a replacement of the constant with a register
@@ -8603,9 +8607,13 @@
(set_attr_alternative "insn_enabled"
[(const_string "yes")
(if_then_else
+ (match_operand:SI 1 "add_operator" "")
+ (const_string "yes") (const_string "no"))
+ (const_string "yes")
+ (if_then_else
(match_operand:SI 3 "mult_operator" "")
(const_string "no") (const_string "yes"))])
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "alu_shift,alu_shift,alu_shift,alu_shift_reg")])
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
=== modified file 'gcc/config/arm/predicates.md'
--- old/gcc/config/arm/predicates.md 2011-05-03 15:14:56 +0000
+++ new/gcc/config/arm/predicates.md 2011-06-22 15:50:23 +0000
@@ -687,3 +687,6 @@
(define_special_predicate "neon_struct_operand"
(and (match_code "mem")
(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
+
+(define_special_predicate "add_operator"
+ (match_code "plus"))
=== modified file 'gcc/config/arm/thumb2.md'
--- old/gcc/config/arm/thumb2.md 2011-06-14 14:37:30 +0000
+++ new/gcc/config/arm/thumb2.md 2011-06-20 12:18:27 +0000
Index: gcc-4_6-branch/gcc/config/arm/thumb2.md
===================================================================
--- gcc-4_6-branch.orig/gcc/config/arm/thumb2.md 2011-09-16 20:22:40.000000000 -0700
+++ gcc-4_6-branch/gcc/config/arm/thumb2.md 2011-09-16 20:28:47.648690433 -0700
@@ -207,7 +207,9 @@
(define_insn "*thumb2_movhi_insn"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
......@@ -93,4 +22,3 @@
"@
mov%?\\t%0, %1\\t%@ movhi
movw%?\\t%0, %L1\\t%@ movhi
2011-07-31 Revital Eres <revital.eres@linaro.org>
gcc/
Backport from trunk -r176970:
* modulo-sched.c: Change comment.
(reset_sched_times): Fix print message.
(print_partial_schedule): Add print info.
=== modified file 'gcc/modulo-sched.c'
--- old/gcc/modulo-sched.c 2011-07-04 12:01:34 +0000
+++ new/gcc/modulo-sched.c 2011-07-31 10:58:46 +0000
@@ -84,13 +84,14 @@
II cycles (i.e. use register copies to prevent a def from overwriting
itself before reaching the use).
- SMS works with countable loops whose loop count can be easily
- adjusted. This is because we peel a constant number of iterations
- into a prologue and epilogue for which we want to avoid emitting
- the control part, and a kernel which is to iterate that constant
- number of iterations less than the original loop. So the control
- part should be a set of insns clearly identified and having its
- own iv, not otherwise used in the loop (at-least for now), which
+ SMS works with countable loops (1) whose control part can be easily
+ decoupled from the rest of the loop and (2) whose loop count can
+ be easily adjusted. This is because we peel a constant number of
+ iterations into a prologue and epilogue for which we want to avoid
+ emitting the control part, and a kernel which is to iterate that
+ constant number of iterations less than the original loop. So the
+ control part should be a set of insns clearly identified and having
+ its own iv, not otherwise used in the loop (at-least for now), which
initializes a register before the loop to the number of iterations.
Currently SMS relies on the do-loop pattern to recognize such loops,
where (1) the control part comprises of all insns defining and/or
@@ -598,8 +599,8 @@
/* Print the scheduling times after the rotation. */
fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
"crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
- INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
- normalized_time);
+ INSN_UID (crr_insn->node->insn), normalized_time,
+ new_min_cycle);
if (JUMP_P (crr_insn->node->insn))
fprintf (dump_file, " (branch)");
fprintf (dump_file, "\n");
@@ -2550,8 +2551,13 @@
fprintf (dump, "\n[ROW %d ]: ", i);
while (ps_i)
{
- fprintf (dump, "%d, ",
- INSN_UID (ps_i->node->insn));
+ if (JUMP_P (ps_i->node->insn))
+ fprintf (dump, "%d (branch), ",
+ INSN_UID (ps_i->node->insn));
+ else
+ fprintf (dump, "%d, ",
+ INSN_UID (ps_i->node->insn));
+
ps_i = ps_i->next_in_row;
}
}
2011-08-09 Revital Eres <revital.eres@linaro.org>
gcc/
Backport from trunk -r176972:
* ddg.c (create_ddg_dep_from_intra_loop_link): Remove
the creation of anti-dep edge from a branch.
(add_cross_iteration_register_deps):
Create anti-dep edge from a branch.
=== modified file 'gcc/ddg.c'
--- old/gcc/ddg.c 2011-07-04 11:00:06 +0000
+++ new/gcc/ddg.c 2011-07-31 11:29:10 +0000
@@ -197,11 +197,6 @@
}
}
- /* If a true dep edge enters the branch create an anti edge in the
- opposite direction to prevent the creation of reg-moves. */
- if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
- create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
-
latency = dep_cost (link);
e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
add_edge_to_ddg (g, e);
@@ -306,8 +301,11 @@
gcc_assert (first_def_node);
+ /* Always create the edge if the use node is a branch in
+ order to prevent the creation of reg-moves. */
if (DF_REF_ID (last_def) != DF_REF_ID (first_def)
- || !flag_modulo_sched_allow_regmoves)
+ || !flag_modulo_sched_allow_regmoves
+ || JUMP_P (use_node->insn))
create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP,
REG_DEP, 1);
2011-08-11 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
gcc/
Backport from mainline:
2011-07-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
* config/arm/vfp.md ("*movdf_vfp"): Handle the VFP constraints
before the core constraints. Adjust attributes.
(*thumb2_movdf_vfp"): Likewise.
=== modified file 'gcc/config/arm/vfp.md'
--- old/gcc/config/arm/vfp.md 2011-01-20 22:03:29 +0000
+++ new/gcc/config/arm/vfp.md 2011-07-27 12:59:19 +0000
@@ -401,8 +401,8 @@
;; DFmode moves
(define_insn "*movdf_vfp"
- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
+ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r, m,w,r")
+ (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
&& ( register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
@@ -418,9 +418,9 @@
gcc_assert (TARGET_VFP_DOUBLE);
return \"fconstd%?\\t%P0, #%G1\";
case 3: case 4:
+ return output_move_vfp (operands);
+ case 5: case 6:
return output_move_double (operands);
- case 5: case 6:
- return output_move_vfp (operands);
case 7:
if (TARGET_VFP_SINGLE)
return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
@@ -435,7 +435,7 @@
"
[(set_attr "type"
"r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
- (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
+ (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else
(eq (symbol_ref "TARGET_VFP_SINGLE")
@@ -449,8 +449,8 @@
)
(define_insn "*thumb2_movdf_vfp"
- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
+ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r ,m,w,r")
+ (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w, mF,r, w,r"))]
"TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
"*
{
@@ -463,10 +463,10 @@
case 2:
gcc_assert (TARGET_VFP_DOUBLE);
return \"fconstd%?\\t%P0, #%G1\";
- case 3: case 4: case 8:
+ case 3: case 4:
+ return output_move_vfp (operands);
+ case 5: case 6: case 8:
return output_move_double (operands);
- case 5: case 6:
- return output_move_vfp (operands);
case 7:
if (TARGET_VFP_SINGLE)
return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
@@ -478,8 +478,8 @@
}
"
[(set_attr "type"
- "r_2_f,f_2_r,fconstd,load2,store2,f_loadd,f_stored,ffarithd,*")
- (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
+ "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
+ (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else
(eq (symbol_ref "TARGET_VFP_SINGLE")
@@ -487,8 +487,8 @@
(const_int 8)
(const_int 4))]
(const_int 4)))
- (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
- (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
+ (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
+ (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
)
2011-08-15 Michael Hope <michael.hope@linaro.org>
Backport from mainline r177357
gcc/testsuite/
2011-08-04 Ian Bolton <ian.bolton@arm.com>
* gcc.target/arm/vfp-1.c: no large negative offsets on Thumb2.
=== modified file 'gcc/testsuite/gcc.target/arm/vfp-1.c'
--- old/gcc/testsuite/gcc.target/arm/vfp-1.c 2011-01-01 08:52:03 +0000
+++ new/gcc/testsuite/gcc.target/arm/vfp-1.c 2011-08-09 23:22:51 +0000
@@ -127,13 +127,13 @@
void test_ldst (float f[], double d[]) {
/* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */
- /* { dg-final { scan-assembler "flds.+ \\\[r0, #-1020\\\]" } } */
+ /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
/* { dg-final { scan-assembler "add.+ r0, #1024" } } */
- /* { dg-final { scan-assembler "fsts.+ \\\[r0, #0\\\]\n" } } */
+ /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\], #0\\\]\n" } } */
f[256] = f[255] + f[-255];
/* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */
- /* { dg-final { scan-assembler "fldd.+ \\\[r1, #-1016\\\]" } } */
+ /* { dg-final { scan-assembler "fldd.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
/* { dg-final { scan-assembler "fstd.+ \\\[r1, #256\\\]" } } */
d[32] = d[127] + d[-127];
}
2011-08-15 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/rs6000/rs6000.c (paired_expand_vector_init): Don't create
CONST_VECTORs with symbolic elements.
(rs6000_expand_vector_init): Likewise.
=== modified file 'gcc/config/rs6000/rs6000.c'
--- old/gcc/config/rs6000/rs6000.c 2011-07-27 18:17:15 +0000
+++ new/gcc/config/rs6000/rs6000.c 2011-08-16 08:59:36 +0000
@@ -5134,7 +5134,9 @@
for (i = 0; i < n_elts; ++i)
{
x = XVECEXP (vals, 0, i);
- if (!CONSTANT_P (x))
+ if (!(CONST_INT_P (x)
+ || GET_CODE (x) == CONST_DOUBLE
+ || GET_CODE (x) == CONST_FIXED))
++n_var;
}
if (n_var == 0)
@@ -5286,7 +5288,9 @@
for (i = 0; i < n_elts; ++i)
{
x = XVECEXP (vals, 0, i);
- if (!CONSTANT_P (x))
+ if (!(CONST_INT_P (x)
+ || GET_CODE (x) == CONST_DOUBLE
+ || GET_CODE (x) == CONST_FIXED))
++n_var, one_var = i;
else if (x != CONST0_RTX (inner_mode))
all_const_zero = false;
2011-08-18 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
Backport from mainline:
2011-08-12 Richard Sandiford <rdsandiford@googlemail.com>
* config/arm/arm.c (get_label_padding): New function.
(create_fix_barrier, arm_reorg): Use it.
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2011-07-04 14:03:49 +0000
+++ new/gcc/config/arm/arm.c 2011-08-12 08:08:31 +0000
@@ -11769,6 +11769,19 @@
return 0;
}
+/* Return the maximum amount of padding that will be inserted before
+ label LABEL. */
+
+static HOST_WIDE_INT
+get_label_padding (rtx label)
+{
+ HOST_WIDE_INT align, min_insn_size;
+
+ align = 1 << label_to_alignment (label);
+ min_insn_size = TARGET_THUMB ? 2 : 4;
+ return align > min_insn_size ? align - min_insn_size : 0;
+}
+
/* Move a minipool fix MP from its current location to before MAX_MP.
If MAX_MP is NULL, then MP doesn't need moving, but the addressing
constraints may need updating. */
@@ -12315,8 +12328,12 @@
within range. */
gcc_assert (GET_CODE (from) != BARRIER);
- /* Count the length of this insn. */
- count += get_attr_length (from);
+ /* Count the length of this insn. This must stay in sync with the
+ code that pushes minipool fixes. */
+ if (LABEL_P (from))
+ count += get_label_padding (from);
+ else
+ count += get_attr_length (from);
/* If there is a jump table, add its length. */
tmp = is_jump_table (from);
@@ -12736,6 +12753,11 @@
insn = table;
}
}
+ else if (LABEL_P (insn))
+ /* Add the worst-case padding due to alignment. We don't add
+ the _current_ padding because the minipool insertions
+ themselves might change it. */
+ address += get_label_padding (insn);
}
fix = minipool_fix_head;
2011-08-18 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
Backport from mainline:
2011-08-18 Richard Sandiford <richard.sandiford@linaro.org>
* config/arm/arm.c (arm_rtx_costs_1): Don't modify the costs of SET.
(arm_size_rtx_costs): Likewise.
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2011-08-12 08:08:31 +0000
+++ new/gcc/config/arm/arm.c 2011-08-18 13:53:37 +0000
@@ -7464,6 +7464,9 @@
*total = COSTS_N_INSNS (4);
return true;
+ case SET:
+ return false;
+
default:
*total = COSTS_N_INSNS (4);
return false;
@@ -7811,6 +7814,9 @@
*total = COSTS_N_INSNS (1) + 1;
return true;
+ case SET:
+ return false;
+
default:
if (mode != VOIDmode)
*total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
2011-08-26 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
Backport from mainline:
2011-08-26 Richard Sandiford <richard.sandiford@linaro.org>
* df-problems.c (df_note_bb_compute): Pass uses rather than defs
to df_set_dead_notes_for_mw.
=== modified file 'gcc/df-problems.c'
--- old/gcc/df-problems.c 2011-07-07 19:10:01 +0000
+++ new/gcc/df-problems.c 2011-08-26 14:32:47 +0000
@@ -3375,7 +3375,7 @@
while (*mws_rec)
{
struct df_mw_hardreg *mws = *mws_rec;
- if ((DF_MWS_REG_DEF_P (mws))
+ if (DF_MWS_REG_USE_P (mws)
&& !df_ignore_stack_reg (mws->start_regno))
{
bool really_add_notes = debug_insn != 0;
2011-09-05 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
gcc/
2011-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
PR target/48328
* config/arm/arm.h (CASE_VECTOR_SHORTEN_MODE): Fix distance
for tbh instructions.
=== modified file 'gcc/config/arm/arm.h'
--- old/gcc/config/arm/arm.h 2011-08-24 17:35:16 +0000
+++ new/gcc/config/arm/arm.h 2011-09-05 14:32:11 +0000
@@ -1961,7 +1961,7 @@
: min >= -4096 && max < 4096 \
? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
: SImode) \
- : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
+ : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
: (max >= 0x200) ? HImode \
: QImode))
2011-09-05 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
Backport from mainline.
2011-08-26 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/cortex-a9.md ("cortex_a9_mult_long"): New.
("cortex_a9_multiply_long"): New and use above. Handle all
long multiply cases.
("cortex_a9_multiply"): Handle smmul and smmulr.
("cortex_a9_mac"): Handle smmla.