In MX6 Arik and Rigel platforms, RGMII tx_clk clock source is from
ENET_REF_CLK pad supplied by phy. To optimize the clk signal path,
the ENET_REF_CLK I/O must have this configuration:
	1. Disable on-chip pull-up, pull-down, and keeper
	2. Disable hysteresis
	3. Speed = 100 MHz
	4. Slew rate = fast

The optimizition make the bias point match the optimum point, which
can maximize design margin.

Signed-off-by: Fugang Duan <B38611@freescale.com>